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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
and enables G20. The output of G21 also
routed to the B input of command register
disables G11.
U53 and also activates G3 which provides
a high to the D input of command register
5 - 2 7 5 .  The Bus Controller senses SACK-N
U53.
and removes SELC-N. G15 is disabled
when PCDA-P is removed and the output of
5 - 2 7 0 .  M10S-P is generated by the CPU
G15 (high) activates G16. The output of
microcode register circuit and E11S-P is
G16 clears FF2 and the 0 output of FF2
generated by the OPIT  emulation instruction
(high) enables gate G8 and activates G17.
register circuit when the CPU is to perform
The output of G17 sets FF4. The 1 output of
a byte read or write operation M10S-P and
FF4 activates G8 and enables gates G14
E11S-P activate gate Gl which provides a
and G18. The output of G8 is inverted by
high to the C input of the command register
inverter 13 which activates G6. The output
U53.
of G6, ONLN-P (waveform E, figure 27),
5 - 2 7 1 . When the CPU is to gain access to
strobes the bus drivers/receivers
U49, gates G5, G7 and G19. ONLN-P is
the INFIBUS, the CPU control circuit gen-
routed to the CPU address register circuit
erates SCMD-P and SCMN-N. SCMD-P
which strobes the address onto the INFIBUS
clocks and loads command register US3 with
address lines.
the desired command data. SCMN-N from
the CPU control circuit ensures that FF5 is
5-276. If command register U53 is loaded
cleared and the 0 outputs of FF3, FF4 and
with a write command, the QB output (high)
FF5 activate gate G21. The output of G21
enables G7 and the QB output (low) enables
enables gate G11.
gate G2 which are activated by the output
of G6. The output of G7 MWOL-N (wave-
5-272. With a read or write command loaded
form F, figure 27) is routed to the CPU ad-
into command register U53, the QD output is
dress recognition circuit which causes data
high and the QD, BSYR-N, output is low.
to be strobed onto the INFIBUS data lines.
The high QD output enables gates G6, G9,
G2 generates RITE-N (waveform G, figure
and G20 and activates G11. The output of
27), on the INFIBUS to indicate that the
G11 disables gates G12 and G15 and sets
data provided is to be written into the ad-
FF2. The 1 output of FF2 activates G9
which enables G12 and G15. The output of
dressed location. If a byte of data is to
be transferred, the QC output of command
G9 also activates gate G10 which generates
register U53 is low and bus drivers/re-
SRLC-N (waveform A, figure 27). SRLC-N is
ceivers U49 also generate BYTE-N (wave-
also inverted by inverter 16 which enables
G14.
form H, figure 27) to indicate a byte is to
be transferred.
5 - 2 7 3 .  The Bus Controller senses SRLC-N
and after granting higher priority INFIBUS
5 - 2 7 7 .  If a read command is loaded in
access requests, the Bus Controller selects
command register U53, the QA output is high
the CPU by generating SELC-N (waveform B,
which enables G5 to be activated by the
figure 27) and PCDA-P (waveform C, figure
output of G6. The output of G5 sets FFl.
27). SELC-N disables G11 which activates
BYTE-N will also be generated, as explained
G12 and enables G15. The output of G12
previously, if byte transfers are to be
disables gate G13 which blocks (traps) the
performed.
precedence pulse.
5 - 2 7 8 .  The output of G8 is also delayed
5 - 2 7 4 .  The precedence pulse, PCDA-P,
by DL2 for 50 nsec and then causes the bus
activates G15 which sets FF3. The 1 output
drivers/receivers to generate STRB-N (wave-
of FF3 enables G16 and G17 and the 0 output
form I, figure 27) and STRB-P (waveform J,
of FF3 disables G4, G10, G19 and G21.
figure 27). STRB-P activates G18 and is
Driver DR1 is also activated by the 0 output
inverted by inverter I5. The output of I5
of FF3 which generates SACK-N (waveform D,
disables G17. The output of G18 clears
figure 27).  Disabling G10 removes SRLC-N
FF3 and the 0 output of FF3 disables DR1,
5-39

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