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 T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
only UB28-P and UB30-P which signifies a
5-264. DNOL-P from the Bus Controller is
normally high and when the CPU is handling
read operation.
interrupts with the Bus Controller, DNOL-P
goes low. When DNOL-P goes low, FFl is
5-259. When the CPU is in the run mode,
set and the 1 output of FFl enables gate G5.
the CPU control circuit generates RBFR-N
When the device number of the interrupting
and RBFS-P. RBFR-N disables G10, G13,
Processor function is placed on the INFIBUS
and G15 which prevents reading from or
writing into the registers. RBFS-P activates
data lines, the Bus Controller generates
gate G21 which activates G20. The output
DNOL-P (high) which activates G5. The
output of G5 activates G3 which generates
of G20, CKEN -P, is routed to and allows
RDCK-P. The output of G5 also activates
the CPU central timing control circuit to
G7 which sets FF2 and DONE-N is generated
continue cycling.
as explained previously.
5-260. To stop cycling the CPU when an
INFIBUS access request cycle is to be
performed by the CPU INFIBUS access cir-
5 - 2 6 6 . General. The CPU INFIBUS access
cuit, SCE3-P is generated by the CPU con-
circuit performs the function of gaining
trol circuit which enables gate G19. When
access to the INFIBUS, on the lowest prior-
the INFIBUS access cycle is initiated, the
ity direct data transfer level (SELC-N), to
INFIBUS access circuit generates BSYR-N
enable the CPU to transfer instructions.
which activates gate G17. The output of
Control data from the CPU microcode reg-
G17 activates G19 which disables G21.
ister circuit specifies a read or write oper-
The output of G21 disables G20 which re-
ation to the CPU INFIBUS access circuit
moves CKEN-P for the time BSYR-N is
and the CPU control circuit instructs the
generated.
CPU INFIBUS access circuit when to initiate
an INFIBUS access request.
5-261. When the INFIBUS access request
by the CPU INFIBUS access circuit is to
5-267. Detail Analysis (see figure 25).
allow the CPU to slave another Processor
When master reset, MRES-N, is generated
function and read data from it, the CPU
on the INFIBUS, the CPU control circuit
INFIBUS access circuit generates RCKL-N.
generates MRST-P and RST2-N. MRST-P
RCKL-N activates G3 which generates
activates gate G4 and the output of G4
RDCK-P. RDCK-P causes the CPU receive
clears the command register, U53. RST2-N
register circuit to read data from the INFIBUS
clears flip-flops FF2, FF3, FF4 and FF5.
data lines.
5-268. M08S-P, MOSS-P and M10S-P from
5-262. When the INFIBUS access request
the CPU microcode register circuit and
by the CPU INFIBUS access circuit is to
E11S-P from the CPU emulation instruction
allow the CPU to slave another Processor
register circuit are the command data bits
function and present data to it, the CPU
that are stored in command register U53.
INFIBUS access circuit *generates MWOL-N.
M08S-P is generated by the CPU microcode
MWOL-N activates G2 which generates
register circuit when the CPU reads from
WOLN-P which causes the CPU receive
an addressed location. M08S-P is routed
register circuit to present data to the
to the A input of command register U53 and
INFIBUS data lines.
activates gate G3. The output of G3 gen-
erates a high to the D input of command
5-263. During read or write INFIBUS access
register U53.
request cycles the slaved Processor func-
tion generates DONE-N. DONE-N is in-
5 - 2 6 9 . MOSS-P is generated by the micro-
verted by inverter I2 which generates and
code register circuit when the CPU writes
routes DUNP-P to the CPU INFIBUS access
into an addressed location. M09S-P is
circuit.
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