CPU CENTRAL TIMING CONTROL CIRCUIT - TM-11-5805-663-14-130093

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5-292. After DL3 delays the high output of

5-288. After the 60 nsec delay of DL3, the

DRl 75 nsec, I4 inverts the high output of

low output of DLl (60) is inverted by inverter

DL3 (75) which removes CKDO-P (waveform

I7 which generates C60A-P (waveform I,

J, figure 28). The low output of I4 resets

figure 28). C60A-P activates gate G3 which

FF2 which removes CKFS-P (waveform N,

resets FF1 which disables G2. At the same

figure 28). After the low output of DRl is

time, the high output of DRl which has been

delayed 150 nsec, DL3 generates Z150-N

delayed 15 nsec by DL3 is inverted by I2

(waveform O, figure 28) which is routed to

which removes CKML-P. With CKML-P

the CPU address recognition circuit. After

removed, G6 is disabled which removes

the high output DRl is delayed 150 nsec,

XSET-N (waveform H, figure 28). The high-

DL3 removes Z150-P (waveform 0, figure 28).

to-low transition output of 12 also triggers

and sets flip-flop FF3 which generates

5 - 2 9 3 . When the CPU is in the halt mode

CKTS-P (waveform K, figure 28) and CKTR-N

and is addressed to perform an operation,

(waveform L, figure 28). CKTS-P is routed

the CPU address recognition circuit generates

to the CPU control circuit and CKTR-N is

CKEN-P (waveform A, figure 28). CKEN-P

routed to the CPU control circuit, CPU

activates gate Gl which triggers and sets

emulation instruction register circuit, and

FFl. Also, if the CPU ALU circuit is to per-

CPU transmit register circuit.

form logical operations rather than arithmetic

operations, the CPU microcode register cir-

5-289. After the 75 nsec delay of DL3, the

cuit generates M32T-P which enables G4.

low output of DL3 (75) is inverted by inverter

The 1 output of FFl activates G2 and the

I4. The output of I4, CKDO-P (waveform J,

CPU central timing control circuit cycles as

figure 28), is routed to the CPU control cir-

explained previously, Also, if data is to be

cuit. At the same time, the high output of

written into a register in the CPU register

DKl which has been delayed 30 nsec by DL3

file circuit, the CPU microcode register

is inverted by 16 which removes CKRD-P

circuit generates M02T-P which enables the

(waveform G, figure 28) and disables G4

set input of FF2. FF2 then generates CKFS-P

and G6. The output of G4 enables G2 and

as explained previously.

G5 and disables G6 which removes XSET-N.

The high-to-low transition output of 16

5-294. When the CPU is in the halt mode

triggers and sets FF4. The output of FF4,

and is addressed to perform an operation,

CKSR-N (waveform M, figure 28) is routed

the CPU address recognition circuit generates

to the CPU sequence register and microcode

CKEN-P (waveform P, figure 28). Also, if an

storage circuits.

arithmetic operation is to be performed by the

CPU ALU circuit, M32T-P is not generated

5-290. After the 90 nsec delay of DL3, the

which disables G4. CKEN-P activates Gl

low output of DL3 (90) disables G3 which

which triggers and sets FFl. The 1 output of

enables G2. If the CPU microcode register

FFl activates G2 and G5. The output of G5,

circuit generates M02T-P, the set input of

CKOO-P (waveform Q, figure 28), is routed to

flip-flop FF2 is enabled. After DL3 delays

the CPU control circuit. The output of G2 is

the high output of DRl 45 nsec, 13 inverts

coupled through DRl and the low output of

the high output of DLl (45) which disables

DRl, CKME-P (waveform R, figure 28), is

G4 and triggers and sets FF2. As a result,

routed to DL3 and the CPU microcode reg-

CKFS-P (waveform N, figure 28) is generated

ister circuit. I8 inverts CKME-P which

and routed to the CPU control circuit and

resets FF4 and generates CMEN-N (waveform

CPU register file circuit.

S, figure 28) which is routed to the CPU

address recognition circuit. CMEN-N also

5-291. After DL3 delays the high output of

disables G5 which removes CKOO-P (wave-

DR1 60 nsec, I7 inverts the high output of

form Q, figure 28). The pulse width of

DL3 (60) which removes C60A-P (waveform I,

CKOO-P is determined by the inherent delays

figure 28). The low output of I7 disables

of G2, DRl, I5, and I8.

G3 and resets FF3 which removes CKTS-P

(waveform K, figure 28) and CKTR-N (wave-

5-295. After DL3 delays the low output of

form L, figure 28).

DR1 15 nsec, I2 inverts the low output of

5-41