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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
DL3 (15) generating CKML-P (waveform T,
put of DRl 45 nsec, I3 inverts the high out-
figure 28) which is routed to the CPU micro-
put of DL3 (45) which triggers and sets FF2.
code register circuit. CKML-P also enables
FF2 generates CKFS-P (waveform BB, figure
G6 and G7. After DL3 delays the low output
28) which is routed to the CPU control cir-
of DRl 30 nsec, I6 inverts the low output of
cuit and CPU register file circuit.  The out-
DL3 (30) generating CKRD-P (waveform U,
put of I3 is also inverted by I1 which en-
figure 28) which is routed to the CPU control
ables Gl (end of cycle).
circuit and CPU register file circuit. CKRD-P
5-300. After DL3 delays the high output of
also activates G6 which generates XSET-N
DRl 60 nsec, I7 inverts the high output of
(waveform V, figure 28). XSET-N is routed
DL3 (60) removing C60A-P (waveform W,
to the CPU register file circuit.
figure 28) which resets FF3. With FF3 reset,
CKTS-P (waveform Y, figure 28) and CKTR-N
5-296. After DL3 delays the low output of
(waveform Z, figure 28) are removed. After
DRl 45 nsec, I3 inverts the low output of
DL3 delays the high output of DR1 75 nsec,
DL3 (45). The output of I3 is inverted by
I4 removes CKDO-P (waveform X, figure 28)
inverter I1 which disables Gl. After DL3
which resets FF2. With FF2 reset, CKFS-P
delays the low output of DRl 60 nsec, I7
(waveform BB, figure 28) is removed. After
inverts the low output of DL3 (60) and gen-
DL3 delays the low output of DRl 150 nsec,
erating C60A-P (waveform W, figure 28)
DL3 generates Zl50-N (waveform CC, figure
which is routed to the CPU control circuit.
28) which is routed to the CPU address re-
C60A-P also activates G3 which resets FFl
cognition circuit. After DL3 delays the
and disables G2. The 1 output of FFl dis-
high output of DRl 150 nsec, DL3 removes
ables G2 and G5.
Z150-N (waveform C, figure 28).
5 - 2 9 7 .  The high output of G2 is coupled
5-301. When the CPU is in the run mode,
through DRl and the high output of DRl is
the CPU address recognition circuit con-
inverted by 15 which removes CKME-P
tinuously generates CKEN-P. Each time G1
(waveform R, figure 28). The low output of
is enabled, CKEN-P will activate Gl which
15 is inverted by I8 which removes CMEN-N
causes the CPU central timing circuit to
(waveform S, figure 28). After DL3 delays
continuously cycle for as long as CKEN-P
the high output of DRl 15 nsec, 12 removes
is being generated by the CPU address
CKML-P (waveform T, figure 28) which dis-
recognition circuit.
ables G6 and triggers and sets FF3. Dis-
abling G6 removes XSET-N. FF3 generates
5-302. CORE MEMORY CONTROLLER AlA3A8
CKTS-P (waveform Y, figure 28) and CKTR-N
COMMAND AND PAGE SELECT
(waveform Z, figure 28) which are routed to
CIRCUIT.
the CPU control circuit.
5-303. General. The Core Memory Control-
5-298. After DL3 delays the low output of
ler command and page select circuit controls
DRl 75 nsec, I4 inverts the low output of
the transfer of data between the Core Memory
DL3 (75) generating CKD0-P (waveform X,
and INFIBUS. It also controls transfers of
figure 28) which is routed to the CPU control
data into selected pages of Core Memory on
circuit.  After DL3 delays the high output of
assigned addresses. The pages are first
DRl 30 nsec, I6 inverts the high output of
selected and stored by the Core Memory Con-
DL3 (30) and removes CKRD-P (waveform U,
troller command and page select circuit.
figure 28) which disables G6 and triggers
When the Core Memory Controller command
and sets FF4. Setting FF4 generates CKSR-N
and page select circuit receives any of the
(waveform AA, figure 28) which is routed to
assigned page addresses (C000 16 through
the CPU sequence register and microcode
DFFF 16), data is transferred into or out of
storage circuits.
the selected page.  One of sixteen pages
may be selected and they all use the same
5-299. After DL3 delays the low output of
assigned page addresses with the variable
DRl 90 nsec, G3 is disabled and its output
being the stored selected page number which
enables G2. After DL3 delays the high out-
is used to modify the address of each page.

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