CPU ADDRESS REGISTER CIRCUIT

T.O.31S5-4-308-l

TM 11-5805-663 -14-13

NAVELEX 0967-464-0010

5-188. The data recirculator U52 recircu-

5-192. CPU ADDRESS REGISTER CIRCUIT.

lates the data stored in transmit shift reg-

isters US1 and U61 when they are shifted

5 - 1 9 3 . General. The CPU address register

left or right. When the CPU ALU input

circuit interfaces the CPU with the INFIBUS

multiplexer circuit generates M12S-P and

address lines to transfer address informa-

M13S-P, the 1C3 (T00S-P) and 2C3 (T15S-P)

tion to or from the INFIBUS. Address infor-

inputs of the data recirculator U52 are

mation from the CPU ALU circuit is stored

coupled to the 1Y and 2Y outputs, respec-

by the CPU address register circuit and

tively. If transmit shift registers US1 and

transmitted to the INFIBUS address lines.

U61 are shifted to the right, T00S-P is

The stored address information is also

routed to the CPU ALU input multiplexer

coupled through data recirculator U52 to

the SDRS (shift right) input of transmit shift

circuit for selection. Address information

on the INFIBUS address lines is received by

are shifted to the left, T15S-P is coupled

the CPU address register circuit and routed

through data recirculator U52 to the SDLS

to the CPU address recognition circuit.

(shift left) input of transmit shift register

5-194. Detail Analysis (see figure 18).

U61. This causes the data stored in trans-

When master reset, MRES-N, is generated

mit shift registers U51 and U61 to be re-

on the INFIBUS, the CPU transmit register

entered into the respective transmit shift

circuit generates RSET-N. RSET-N clears

address registers U6, U16, U26 and U36,

and presets flip-flops FFl and FF2. A16R-N

5 - 1 8 9 . When the CPU ALU input multi-

and A17R-N are generated by FFl and FF2,

plexer circuit generates M12S-P, data re-

respectively, and routed to the CPU emu-

circulator U52 couples the 1Cl and 2C 1

lation instruction register circuit.

inputs (CRYS-P) to the 1Y and 2Y outputs,

respectively. When shifting transmit shift

5-195. The CPU ALU circuit generates

registers US1 and U61 left or right, each

LB00-P through LB15-P which is routed to

successive low to high transition of CKTR-N

the inputs of the address registers U6, U16,

cause the associated data bit to assume

U26 and U36. When the CPU control cir-

the high or low level of CRYS-P.

cuit generates ARCK-P, the address regis-

ters are clocked and loaded with the LB00-P

5-190. When the CPU ALU input multiplex-

through LB15-P address information.

er circuit generates M13S-P, data recircu-

LB00-P is routed to the set and clear inputs

lator U52 couples the lC2 and 2C2 inputs

of FF2 and LBOl-P is routed to the set and

(ground) to the 1Y and 2Y outputs, respec-

clear inputs of FFl. When the CPU control

tively. When shifting transmit shift reg-

circuit generates SCM2-N, FFl and FF2 are

isters U51 and U61 left or right, each suc-

set or cleared depending on the levels of

cessive low to high transition of CKTR-N

LB00-P and LB0l-P.

causes the associated data bit to return

to logic 0.

5 - 1 9 6 . The address information stored in

address registers U6, U16, U26, and U36

5-191. With M12S-P and M13S-P both low,

is routed to bus drivers/receivers U10, U20,

data recirculator U52 couples the 1C0

U30, and U40 (Gl shown typical). When

(Tl5S-P) and 2CO inputs (ground) to the 1Y

ONLN-P is generated by the CPU INFIBUS

and 2Y outputs, respectively. When shifting

access circuit, the address bus drivers/

the transmit shift registers U51 and U61

receivers are activated which generates

left, each successive low to high transition

AB00-N through AB15-N. Address registers

of CKTR-N causes the associated data to

U6, U16, U26 and U36 also generate A00S-P

return to logic 0. If shifting the transmit

through A15S-P, which is routed to the CPU

shift register U51 and U61 right, each suc-

ALU input multiplexer circuit.

cessive low to high transition of CKTR-N

5 - 1 9 7 . When an address is on the INFIBUS

causes the associated data to assume the

address lines, the address bus drivers/

present value of Tl5S-P.

5-30