CPU TRANSMIT REGISTER CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

data stored by the CPU transmit register

CPU transmit register

circuit is also transmitted to the CPU ALU

onto the 1NFIBUS data

input multiplexer circuit for selection.

e INFIBUS is stored by

ter circuit for use by

5-183. Detail Analysis (see figure 17).

Data stored by the CPU receive

When master reset, MRES-N, is generated

circuit is routed to the CPU ALU

on the INFIBUS, inverter I1 inverts MRES-N

ltiplexer circuit.

and the output of I1 is inverted by inverter

I2 which generates RSET-N. RSET-N clears

etail Analysis (see figure 16).

the transmit shift registers U51 and U61

set, MRES-N, is generated

and is routed to and clears the CPU address

transmit register

recognition circuit, CPU address register

which clears the

circuit and CPU receive register circuit.

69 and U79. Data

receivers U50, U60, U70 and

5-184. Data, LBOO-P through LB15-P, from

er 12 typical) inverts the data,

the CPU ALU circuit, is routed to the paral-

present on the

lel inputs of transmit shift registers U51

enerate DAOO-P

and U61. When the CPU control circuit

hich is routed to receive

generates STSL-P and STSR-P, a low to high

rs U59, U69 and U79. When the

transition of CKTR-N from the CPU central

slaved to read data present on the

timing control circuit causes transmit shift

S data lines, the CPU address recgo-

registers U51 and U61 to be loaded with the

nition circuit generates RDCK-P which loads

parallel data, LBOO-P through LBl5-P.

the receive registers U59, U69 and U79

Transmit shift registers U51 and U61 store

with DAOO-P through DA15-P. The receive

the data and generate T00S-P through T15S-P

registers U59, U69 and U79 store the data

which are routed to the inputs of the trans-

and generate ROOS-P through R15S-P which

mit data bit selector U62 and to the CPU

are routed to the CPU ALU input multiplexer

receive register circuit and CPU ALU input

circuit for selection. ROOS-P is also routed

multiplexer circuit.

to the CPU control circuit for testing.

5-180. When the CPU is slaved to read

5-185. The CPU ALU input multiplexer cir-

out data or when the CPU is slaving

cuit generates a binary code comprised of

another Processor module and providing

M12S-P through M15S-P which causes the

data, the CPU transmit register circuit gen-

transmit data bit selector to select one of

erates TOOS-P through T15S-P. Inverters I2

the sixteen data bits, TOOS-P through

through I17 invert TOOS-P through T15S-P

T15S-P. If the selected bit position is high,

and the data is routed to data bus driver/

the transmit data bit selector transmits

receivers U5O, U60, U70, and U80.

BITl-N to the CPU control circuit.

TOOR-N and T15R-N are also routed to the

CPU emulation instruction register circuit

5-186. When the CPU control circuit gen-

to modify the fields within the microcode

erates STSL-P, the S1 inputs of transmit

word. When the CPU address recognition

shift registers U51 and U61 are disabled.

circuit generates WOLN-P, the data bus

This causes transmit shift registers U51

and U61 to shift the stored data to the left

driver/receivers U50, U60, U70 and U80

(QH to QA) on each successive low to high

are strobed which generates DBOO-N through

transition of CKTR-N.

DB15-N.

5-181. CPU TRANSMIT REGISTER CIRCUIT.

5-187. When the CPU control circuit gen-

erates STSR-P, the SO inputs transmit shift

5-182. Genera 1. The CPU transmit register

registers U51 and U61 are disabled. This

circuit stores the data to be strobed to the

causes transmit shift registers U51 and U61

INFIBUS data lines. It also receives data

to shift the stored data to the right (QA to

from the CPU ALU circuit and transmits data

QH) on each successive low to high transi-

to the CPU receive register circuit, The

tion of CKTR-N.

5-29