CPU ALU INPUT MULTIPLEXER CIRCUIT

T.O.31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

A15S-P data from the CPU address register

receivers invert AB00-N through ABl5-N and

circuit to generate Y00A-P through Yl5A-P,

generate BA0l-P through BAl5-P. The inverse

as required, which are routed to the CPU

of AB00-N is not used. BA01-N through

ALU circuit.

BAO4-P are routed to the CPU emulation

instruction register circuit and BAO5-P

5-204. When the CPU microcode register

through BAl5-P are routed to the CPU ad-

circuit generates Ml6S-P and M17S-P, the

dress recognition circuit.

lC3 and 2C3 inputs of the 8 multiplexers

are selected and coupled to the 1Y and 2Y

5-198. CPU ALU INPUT MULTIPLEXER

outputs, respectively. This causes the

CIRCUIT.

M04S-P through M11S-P data from the CPU

microcode register circuit to generate

5 - 1 9 9 . General. The CPU ALU input multi-

Y00S-P through YO7S-P and YO8S-P through

plexer circuit selects an operand (16-bit

Yl5S-P, as required, which are routed to

word) from either the CPU transmit register

the CPU ALU circuit. Y08S-P through

circuit, CPU receive register circuit, CPU

Y15S-P are identical to Y00S-P through

address register circuit, or an 8-bit word

Yl5S-P in this case.

from the CPU microcode register circuit.

5 - 2 0 5 . Gates Gl through G4 are enabled

5-200. Detail Analysis (see figure 19).

by Ml6S-P and M17S-P and all of the gates

Multiplexers U7, U8, U17, U18, U27, U28,

may be activated simultaneously or individ-

U37 and U38 are each dual 4-line-to-l-line

ually by M12S-P through M15S-P from the

data selectors which selects data as deter-

CPU microcode register circuit. M12S-P

mined by the binary code at the A and B

through M15S-P are also routed to the CPU

inputs of the multiplexers. Ml6S-P and

transmit register circuit and M12S-P is also

M17S-P from the CPU microcode register

routed to the CPU ALU carry and overflow

circuit are routed to all 8 multiplexers A

circuit.

and B inputs and determine which data is

selected.

5 - 2 0 6 . If M12S-P and M13S-P are gener-

ated by the CPU microcode register circuit,

5 - 2 0 1 . When M16S-P and M17S-P, from

G2 and G4 are activated which disables

the CPU microcode register circuit are low,

multiplexers U8, U18, U28, and U38. The

the ICO and 2C0 inputs of the 8 multiplex-

M04S-P through M11S-P data from the CPU

ers are selected and coupled to the 1Y and

microcode register circuit generates Y08A-P

2Y outputs, respectively. This causes the

through Yl5A-P, as required, and Y00A-P

R00S-P through Rl5S-P data from the CPU

through YO7A-P will all be low.

receive register circuit to generate Y00A-P

through Y15A-P, as required, which are

5-207. If M14S-P and M15S-P are generated

routed to the CPU ALU circuit.

by the CPU microcode register circuit, Gl

and G3 are activated which disables multi-

5 - 2 0 2 . When the CPU microcode register

plexers U7, U17, U27, and U37. The

circuit generates M17S-P, the 1Cl and 2Cl

M04S-P through M11S-P data from the CPU

inputs of the 8 multiplexers are selected and

microcode register circuit generates Y00A-P

coupled to the 1Y and 2Y outputs, respec-

through Y07A-P, as required, and Y08A-P

tively. This causes the T00S-P through

through Y15A-P will all be low. Also, only

T15S-P data from the CPU transmit register

gate Gl, G2, G3 or G4 will be activated and

circuit to generate Y00A-P through Y15A-P,

its associated multiplexers disabled. The

as required, which are routed to the CPU

M04S-P through MlSS-P data from the CPU

ALU circuit.

microcode register circuit will be coupled

through the multiplexers that are enabled.

5-203. When the CPU microcode register

circuit generates Ml6S-P, the lC2 and 2C2

5-208. CPU ALU CIRCUIT.

inputs of the 8 multiplexers are selected

and coupled to the 1Y and 2Y outputs, re-

5-209. Genera 1. The CPU ALU circuit per-

spectively. This causes the A00S-P through

forms one of sixteen logical functions or one

5-31