CPU MICROCODE REGISTER CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

through UB17-P from the CPU sequence

5-157. CPU MICROCODE REGISTER

CIRCUIT.

5-158. General. The CPU microcode req-

5-162. CKML-P from the CPU central tim-

ister circuit stores and generates the 36-bit

ing control circuit, and DNTS-P from the

CPU control circuit activates gate G2 which

microcode word for decoding by the various

generates CLRM-N. CLRM-N clears micro-

CPU circuits. The 36-bit microcode word

controls all CPU generations. The CPU

code registers U33 through U40.

microcode register circuit receives the

microcode word from the CPU sequence

5-163. CKML-P, from the CPU central

timing control circuit, is also routed to the

emulation instruction register circuit, and

clock (CLK) inputs of microcode registers

CPU address recognition circuit stores the

U37, U38, and U40 which loads the data

microcode word. The CPU microcode reg-

inputs into the microcode registers U37,

ister circuit then generates control signals,

U38, and U40. CKME-P from the CPU

specified by the microcode word, which are

central timing control circuit is routed to

the clock (CLK) inputs of microcode registers

decoded by the CPU control circuit, CPU

U33 through U36 and U39 which loads the

tion register circuit, CPU central timing

data input into the microcode registers U33

control circuit, CPU ALU circuit, CPU

through U36 and U39.

sequence register and microcode storage

circuit, CPU ALU input multiplexer circuit,

5 - 1 6 4 . Microcode registers U37, U38, and

and CPU INFIBUS access circuit.

U40 generate the following: MOOT-P, MOlT-P

M02T-P, MOOF-N, MOlF-N, M18T-P through

5-159. Detail Analysis (see figure 14).

M31T-P. If the QF output of microcode

When the master reset pulse, MRES-N, is

generated on the INFIBUS, the CPU control

generates M32T-P.

circuit generates RST2-N which activates

gate Gl. Gl generates M32T-P which is

5 - 1 6 5 . Microcode registers U33 through

routed to the CPU ALU circuit and CPU

U36, and U39 generate the following:

central Timing Control circuit.

M03S-P through M17S-P, M04R-N, MOSR-N,

5-160. UBOO-P, UBOl-P, UB02-P, UB18-P

M12R-N through M14R-N, M20S-P through

through UB25-P, and UB28-P through UB32-P,

M23S-P, M22R-N, M23R-N, M26S-P,

from the CPU sequence register and control

M27S-P, M33S-P through M35S-P, and

storage circuit are routed to the respective

M33R-N through M35R-N.

data inputs of microcode registers U37,

U38, and U40. UB03-P through UB17-P,

5 - 1 6 6 . The CPU microcode register circuit

UB20-P through UB23-P, UB26-P and

routes the following bits to the CPU control

UB27-P, and UB33-P through UB35-P are

circuit: M00F-N, MOOT-P, MOlF-N,

r o u t e d to the respective d a t a inputs o f

MOLT-P, M22T-P through M25T-P, M23F-N,

microcode registers U33, U34, U35,

U36,

M22F-N, M20T-P, M2lT-P, M08S-P through

and U39 and CPU Central Timing Control

MlOS-P, M12S-P through Ml5S-P, M12R-N,

circuit.

M14R-N, M33S-P through M35S-P, and

5-161. UB20-P through UB23-P from the

M33R-N through M35R-N. The CPU micro-

CPU emulation instruction register circuit

code register circuit routes the following

are wire-anded with UB20-P through UB23-P

bits to the CPU emulation instruction reg-

from the CPU sequence register and control

ister circuit for decoding: M18T-P, M19T-P,

storage circuit. UB02-P, UB28-P, and

M03S-P through M11S-P, M04R-N, and

UB30-P from the CPU address recognition

M05R-N. M04S-P through Ml7S-P are routed

circuit are wire-anded with UB02-P, UB28-P,

from the CPU microcode register circuit to the

and UB30-P from the CPU sequence register

CPU ALU input multiplexer circuit for de-

and control storage circuit. UB04-P through

coding. M28T-P through M32T-P are routed

UB15-P from the CPU emulation instruction

from the CPU microcode register circuit to the

CPU ALU circuit for decoding. M04S-P

5-27