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Page Title:
CPU SEQUENCE REGISTER AND CONTROL STORAGE CIRCUIT. |
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 T.O. 31S5-4-308-l
TM 11-5805-663-14-l3
NAVELEX 0967-464-0010
U44 goes high which enables sequence
ATLD-N. The 1 output of FF2 holds ST2
activated which prevents the LFRQ-N input
register/counter U43 to count. On the
sixteenth count, sequence register/counter
from triggering ST2. During any interrupts
U43 count increases by one, the sequence
cycled by the Bus Controller service re-
register/counter U44 resets and the CRY
quest selection and interrupt circuit,
output returns low. The cycle is repeated
INTR-N will be generated. INTR-N disables
until a count of 255 is reached, then both
G15, and presets FF2. The 0 output of FF2
now disables Cl1 and the 1 output of FF2
sequence register/counters U43 and U44
reset to 0. If SCM1-N is generated, both
enables ST2 to be triggered by LFRQ-N.
sequence register/counters are prevented
FF2 will remain in this state until RSET-N
from counting.
is once again generated by MRES-N.
5-149. Oscillator Y2 generates a 25 MHz
5 - 1 5 4 . The CPU microcode register circuit
symmetrical square wave signal which is
generates M04S-P through M11S-P which
coupled to the INFIBUS by driver DR2, gen-
are applied to the parallel inputs of sequence
erating CLKA-N, CLKA-N is used by Proc-
register/counters U43 and U44. When the
essor functions for synchronizing and tim-
CPU control circuit generates SS07-N, the
ing purposes.
load inputs of sequence register/counters
U43 and U44 are enabled. On the next low
to high transition of CKSR-N, sequence
CONTROL STORAGE CIRCUIT.
register/counters U43 and U44 are clocked
and loaded with the parallel data which
5-151. General. The CPU sequence regis-
specifies a jump address.
ter and control storage circuit contains the
CPU microprogram which controls the oper-
5-155. SOOS-P through SO7S-P from se-
ation of the CPU. The sequence register
quence register/counters U43 and U44,
addresses the control storage ROMS
address the microcode words within the
which generates microcode words which
control storage ROMS. The control storage
are stored in the CPU microcode
ROMS consist of nine 256 word 4-bit ROMS
register circuit.
which generate 256 36-bit words. UBOO-P
through UB35-P are routed to the CPU
5 - 1 5 2 . Detail Analysis (see figure 13).
microcode register circuit for storage.
When the master reset, MRES-N, is gen-
erated on the INFIBUS, the CPU control
5 - 1 5 6 . The microcode word is divided into
circuit generates RST2 -N which enables
13 fields. The bit positions that make up
the clear (CLR) inputs of the sequence
the various fields are as follows:
register/counters U43 and U44. On the
next low to high transition of CKSR-N from
the CPU central timing control circuit, the
- IELD
F - -
BIT POSITION
sequence register/counters U43 and U44
are clocked and cleared.
w
0-2
5 - 1 5 3 . The sequence register/counters
Z
3
U43 and U44 are 4-bit presettable binary
L1
4-7
counters. They are cascaded to form an
L2
8-11
8-bit presettable binary counter which
M
12-15
counts from 0 to 255 (binary). When the
Y
16,17
F
CPU is in the run mode, the CPU control
18,19
X
circuit generates RBFS-P which enables
20-23
D
sequence register/counter U44 to count.
24,25
C
On each low to high transition of CKSR-N,
26,27
A
sequence register/counter U44 count in-
28-31
T
creases by one. On the fifteenth count,
32
S
the CRY output of sequence register/counter
33-35
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