BUS CONTROLLER A1A3A5 ALARM AND INFIBUS TIMING CIRCUIT-CONT.

T.O.

31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

form N, figure 11) are generated, NINT-N

interrupt will be completed within 300 nsec

and NNTS-P (waveform Q, figure 11) are

and, as explained previously, G2 is acti-

also generated by the Bus Controller service

vated by the output of ST1 which activates

request selection and interrupt circuit.

G3. The output of G3 triggers SSl and its 1

NINT-N enables gate G22 and when FF12

output (waveform B, figure 12) triggers SS2

is set, G37 is activated which generates

which triggers SS3. The 0 output of SSl

PSAK-N; PSAK-N disables G20 which

activates G2 once again and the cycle re-

removes DNOL-P. PSAK-N also activates

peats with every PWST-N pulse. SS2 resets

G22 which activates G23. The output

in 250 usec and will be triggered again in

of G23 activates G19 which causes SACK-N

2.5 msec (waveform C, figure 12) which

(waveform D, figure 11) to go low. NNTS-P

retriggers SS3 The 1 output of SS3 (wave-

(waveform R, figure 11) goes high which

form D, figure 12) enables G8 and every

enables G28. SCLK-P goes high triggering

250 usec SS2 resets which activates G8.

internal interrupt flip-flops U68 which sets

The output of G8 activates G9 which gen-

the associated flip-flop as determined by

erates MRES-N (waveform E, figure 12).

which alarm (EXAT-N, LFRQ-N, PWST-N power

MRES-N is generated for 2.5 msec and-is

fail, PF-N, or power restart, PR-N) has been

removed for 250 usec.

generated. SCLK-P also activates gate G15

which activates gate G14. The output of

5-146. if regulated power is only lost

G14, RS-N, clears FF3, FF5, FF6, and

momentarily and then recovers, G10 will be

FF7. The outputs of the internal interrupt

disabled after SS3 resets and the pulse gen-

flip-flops U68 are routed to the bus drivers

erating network, C6 and R9, generates a

U58. Gate G16 receives the EXAT-N and

100 nsec pulse that generates the autoload,

LF-N outputs of internal interrupt flip-flops

ATLD-N (waveform G, figure 12), pulse, as

U68 which enables gate G17 of data bus

explained previously. ATLD-N is only gen-

driver U58. When ONLN-P (waveform 0,

erated if PRAL-N is low which is determined

figure 11) is generated by G40, G28 will be

by a switch in the Program Maintenance

activated which strobes data bus drivers

Panel. If PRAL-N is high, the output of

U58 and enables gate G29. Also, I5 in-

inverter I1 disables G11 and ATLD-N is not

verts ONLN-P which generates HOLD-N

generated. If the PRIN-N, power restart

(waveform P, figure 11) via G30 and DR4.

interrupt inhibit signal, is not generated

Data bus drivers U58 generate the device

(high) by the Program Maintenance Panel,

number, binary code of DBOO-N through

G4 will be enabled for a power restart inter-

DB03-N which represents the alarm gen-

rupt. When pulse generating network C6

erated, to the INFIBUS data lines. For an

and R9 generates the 100. nsec pulse, G4 is

external attention, EXAT-N (CPU level I

activated which generates PR-N (waveform

self-interrupt) or line frequency, LFRQ-N

H, figure 12), setting FF6. The 1 output of

(CPU level 4 self-interrupt), DBOO-N goes

FF6 is routed to its associated internal

low. For a power restart, PR-N, level 4

interrupt flip-flop U68. The 0 output of

interrupt DB02-N is generated. For power

FF6 activates G18 which generates DNUM-P

fail, PF-N, level 4 interrupt DB0l-N is

level 4 interrupt request. DNUM-P is

generated. G29 is activated after the

routed to the Bus Controller service request

delay of DL4 which generates STRB-N

selection and interrupt circuit.

(waveform G, figure 11). When PSAK-N

goes high G20 is activated and G22 is dis-

5-147. DNUM-P and DN3R-N request a

a bled. G20 generates DNOL-P, device

level 4 and a level 1 interrupt, respectively,

number on line, which is routed to the CPU

and these interrupts are generated internal-

and G22 causes SACK-N to go high via G19

ly by the Bus Controller alarm and INFIBUS

and G23. The remainder of the cycle is the

timing circuit. The interrupt cycles for

same as explained previously.

these internal interrupts are similar to the

Processor function interrupts except for the

5 - 1 4 8 . When MRES-N is generated,

following. During the cycle, as PCDI-P

RSET-N is generated which clears FF2. The

(waveform B, figure 11) and CYST-N (wave-

0 output of FF2 enables G10 to generate

5-25