BUS CONTROLLER A1A3A5 ALARM AND INFIBUS TIMING CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

a cycle with Core Memory. The 0 output of

5-143. The external attention signal,

FF10 holds G30 activated.

EXAT-N, from the INFIBUS is generated by

the Program Maintenance Panel to interrupt

the CPU (CPU level 1 self-interrupt).

5-141. The selected Processor function

EXAT-N sets flip-flop FF7 and the 1 output

generates SACK-N (waveform D, figure 11),

of FF7 is routed to its associated internal

I3 inverts SACK-N and generates RSAK-P

interrupt circuit to request a level 1

which is routed to the Bus Controller ser-

interrupt. This paragraph does not apply

vice request selection and interrupt circuit.

to TDCS.

The Bus Controller service request selec-

tion and interrupt circuit removes S11P-P,

PCDI-P and CYST-N, and generates RNIR-P,

5-144. LFRQ-N is generated by the PFD/

INAR-N, INTR-N and SCLK-P. When

Clock once every 40 msec and is used to

PCDB-P goes low, G31 is disabled. The

update the calendar and clock program

high output of G31 activates G32. The out-

stored in Core Memory (CPU level 4 self-

put of G32 clears FF11 which disables G31.

interrupt). If the LFRQ-N interrupt inhibit

RNIR-P enables G20 and INAR-N disables

input, LFIN-N, from the Program Mainte-

G33. The Processor function generating

nance Panel is low, gate G1 is enabled.

the interrupt presents its device number

LFRQ-N triggers Schmitt trigger ST2 and the

and strobe on the INFIBUS. The strobe,

pulse generating network, C5 and R5,

STRB-N (waveform G, figure 11), is inverted

generates a 100 nsec pulse which activates

by 16 which generates RSTR-P. RSTR-P

G l . The output of Gl sets FF3. The 1 out-

activates G36 which clears FF12, and dis-

put of FF3 is routed to its associated inter-

ables G37. The 1 output of FF12 disables

nal interrupt flip-flop U68. The 0 output of

G32 and the 0 output enables G33. Dis-

FF3 activates gate G18 which generates

abling G37 causes PSAK-N to go high which

DNUM-P. DNUM-P is routed to the Bus

activates G20. The output of G20), DNOL-P

Controller service request selection and

(waveform M, figure 11) is routed to the

interrupt circuit to request a level 4 inter-

CPU. DNOL-P indicates to the CPU that

rupt.

the Processor function requesting INFIBUS

access has placed its device number on

5-145. Power status, PWST-N (CPU level 4

the INFIBUS.

self-interrupt), is held high to indicate

regulated power is available. PFD/Clock

5-142. Normally, DONE-N (waveform I,

logic activates this signal 2.2 to 3.0 msec

figure 11) is generated by the selected

before loss of regulation due to a power

Processor function to indicate a completed

failure. The power fail interrupt has an

data transfer. DONE-N is inverted by

inhibit input, PFIN-N, generated by the

inverter I9 which activates G39. Inverter

Program Maintenance Panel to inhibit a

I10 inverts the output of I9 and disables

level 4 interrupt request (PFIN-N disables

gate G7 when low). When PFIN-N is high,

gate G38 and G34. The output of G39 sets

G7 is enabled. When there is loss of reg-

FF14 and activates G40. The 1 output of

ulated power, PWST-N will be generated.

FF14 enables G38, and the 0 output disables

PWST-N (waveform A, figure 12) is a 9.6KHz

G41. When DONE-N returns to high, I9

pulse train which activates ST1. The out-

disables G39 which disables G40, removing

put of ST1 activates gate G6 which activates

ONLN-P; The output of I10 activates G38

G7, G7 generates PF-N (waveform F, fig-

which clears FF13. The 1 output of FF13

ure 12) which sets FF5. The 1 output of

disables G35, G36, G39 and G41 and clears

FF5 is routed to its associated internal

FF14. The selected Processor function re-

interrupt flip-flop U68. The 0 output of

moves STRB-N, the QUIT-N timing is dis-

FF5 activates G18 which generates DNUM-P

abled, and the Bus Controller alarm and

a level 4 interrupt request. DNUM-P is

INFIBUS timing circuit is cleared to its

routed to the Bus Controller service request

initial condition as explained previously

selection and interrupt circuit. The level 4

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