BUS CONTROLLER A1A3A5 ALARM AND INFIBUS TIMING CIRCUIT-CONT.

T.O. 31S5-4-308-l

T M 11-5805-664-14-13

NAVELEX 0967-464-0010

and clears the INFIBUS to allow other func-

PCDI-P (waveform B, figure 11) is generated

tions to be serviced. Normally, within 2

which enables gate G12. PCDI-P is delayed

usec, DONE-N (waveform I, figure 11) is

by delay DL2 for 20 nsec and then activates

generated by the serviced Processor function

G12. The output of G12 is inverted by in-

to indicate a completed data transfer. STRB-N

verter I2, generating PCDE-P which activates

is removed. The removal of STRB-N re-

gate G13 and enables gate G24. The output of

moves RSTR-P and RSTN-N which activates

G12 is also delayed by delay DL3 for 50 nsec.

G26, clearing FF8. The 0 output of FF8

The output of DL3 disables G13. G13 gener-

ates the precedence pulse PCDB-P (waveform

(high) is inverted by I4 which disables G27.

C, figure 11). If SACK-N is not received

The Bus Controller alarm and INFIBUS

from the selected Processor function within

timing circuit returns to its initial condi-

tions as explained previously.

2 usec, SS5 resets which activates G24.

The output of G24 activates gate G23 which

5-140. With an interrupt being cycled by

activates gate G19, generating SACK-N.

the Bus Controller service request selection

SACK-N prevents the selected function from

and interrupt circuits, the Bus Controller

being serviced and aborts the cycle which

alarm and INFIBUS timing circuits supports

clears the INFIBUS to allow other Processor

functions to be serviced. Normally, within

the cycle with additional signals. The nor-

ma1 internal SACK-N and QUIT-N timing is

25 to 350 nsec after PCDA-P is generated,

SACK-N (waveform D, figure 11) is generated

involved as explained previously and in

by the selected Processor function. Inverter

addition, HOLD-N and DNOL-P are gener-

13 inverts SACK-N, generating RSAK-P (wave-

ated for the CPU to read the interrupting

form E, figure 11) which is routed to the

Processor function device number. As an

Bus Controller service request select and

interrupt is initiated, SCRS-N (waveform J,

interrupt circuit. NSAK-N (waveform F,

figure 11) is generated by the Bus Controller

service request selection and interrupt cir-

service request select and interrupt circuit

cuit which resets the internal interrupt flip-

and S11P-P and PCDI-P are removed. NSAK-N

flops U68. Also, at the same time, RNIR-P

disables gate G25 and with PCDI-P removed,

(waveform K, figure 11) and INAR-N (wave-

PCDE-P is also removed. RSAK-P also acti-

form L, figure 11) are removed. With RNIR-P

vates gate G21 which triggers single shot SS4

low, G20 is disabled which removes DNOL-P

which will be set for 2 usec. The output of

(waveform M, figure 9). With INAR-N high,

G33 is activated which sets FF11 and the 1

G21 also sets flip-flop FF9. The output of

SS4 sets flip-flop FF8. The 0 output of FF8

output of FF11 enables G31. CYST-N (wave-

is inverted by inverter 14 which enables

form N, figure 11) is generated after S11P-P

G27.

(waveform A, figure 11) and PCDI-P (wave-

form B, figure 11) are generated. G33 is

5-139. 20 to 30 nsec after SACK-N is gen-

disabled by CYST-N and the output of G33

erated, the selected Processor function

enables G31. PCDB-P is generated at this

presents its data and 50 nsec later its strobe

time and G31 is activated. The output of

on the INFIBUS. The strobe, STRB-N (wave-

G31 sets FF12 which enables gate G32,

form G, figure 11), is inverted by inverter I6,

disables G33, and activates gates G34 and

generating RSTR-P. RSTR-P is inverted by

G37. The output of G34 sets FF13 and

inverter I8, generating RSTN-N. RSTN-N

activates gate G40. G37 generates PSAK-N

disables G26 and G21 which clears FF9.

which disables G20. The 1 output of FF13

The 0 output of FF9 enables G26. 20 to 30

enables gates G35, G36 and G39 and acti-

nsec after STRB-N is received, SACK-N is

vates gate G41 which activates G40. The

removed which removes RSAR-P and NSAK-N.

output of G40, ONLN-P (waveform 0, fig-

If the service cycle is not completed within

ure 11), enables gate G28. ONLN-P is

2 usec after SACK-N is generated, SS4 resets

also inverted by inverter I5 which activates

which activates G27. The output of G27 is

G30 and sets flip-flop FF10. The output of

coupled through bus drive: receivers U28

G30 is coupled through driver DR4, which

which generates QUIT-N (waveform H, fig-

generates HOLD-N (waveform P, figure 11).

ure 11). QUIT-N aborts the service cycle

HOLD-N prevents the CPU from performing

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