BUS CONTROLLER A1A3A5 ALARM AND INFIBUS TIMING CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5-132.

BUS CONTROLLER A1A3A5 ALARM

put (waveform E, figure 9) activates gate

AND INFIBUS TIMING CIRCUIT.

G10 and enables gate G8. Each time SS2

resets, G8 is activated which activates G9.

5 - 1 3 3 . G e n e r a l . The Bus Controller alarm

and INFIBUS timing circuit monitors alarm

5-136. After 70 msec, the output of DLl

inputs, generates internal interrupts, and

goes high and ST1 is disabled which dis-

generates assigned device numbers for the

ables G2. In addition, the high output of

internal interrupts. When INFIBUS requests

DLl disables G9 which removes MRES-N

are cycled, the Bus Controller monitors the

and after 250 usec SS2 resets. The 0 out-

cycles and aborts them if they are not com-

put of SS2 (high) activates G8 which acti-

pleted within predetermined time limits.

vates G9, generating MRES-N a second

time for 190 msec. After 190 msec, SS3

5 - 1 3 4 . Detail Analysis (see figure 8).

resets and disables G8 which disables G9,

When 5 volts AC power is applied, the out-

removing MRES-N. T h e 1 o u t p u t o f S S 3 ( l o w )

put of delay DL1 (waveform A, figure 9)

d i s a b l e s G10 and the low-to-high transition

remains low for 70 msec which activates

output of G10 activates the pulse generator

gate G9. G9 generates the master reset

C6 and R9, generating a 100 nsec pulse

pulse, MRES-N (waveform F, figure 9). The

(waveform H, figure 9). The 100 nsec

output of G9 is also coupled through driver

pulse activates G11 and DRl which gen-

DR3 which generates RSET-N (waveform J,

erates the autoload pulse, ATLD-N (wave-

figure 9). RSET-N resets flip-flop FF2 which

form I, figure 9).

enables gate G11. RSET-N also activates

gate G14. The output of G14, RS-N, clears

5-137. Master reset, MRES-N can be gen-

flip-flops FF3, FF5, FF6, and FF7. RSET-N

erated at any time by touching the reset

also clears flip-flops FF11, FF12, FF13, and

p u s h b u t t o n on t h e P r o g r a m M a i n t e n a n c e

FF14. The Bus Controller service request

P a n e l . This generates REPB-N (waveform

select and interrupt circuit then generates

A , figure 10) w h i c h d i s a b l e s g a t e G 5 a n d

SCRS-N (waveform K, figure 9) which

resets flip-flop FFl. The 1 output of FFl

clears the internal interrupt flip-flops U68

(low) activates G3 which triggers SSl. SS1

(FF7 shown typical). Also, RNIR-P (waveform

resets in 2.5 msec and the 1 output of SS1

L, figure 9), and INAR-N (waveform M,

(waveform B, figure 10) triggers SS2. The

figure 9) are received from the Bus Controller

1 output of SS2 (waveform C, figure 10)

service request selection and interrupt circuit

triggers SS3 and the 1 output of SS3 (wave-

RNIR-P activates gate G20 which generates

form D, figure 10) enables G8 and G10.

DNOL-P and INAR-K disables gate G33.

After 250 usec, SS2 resets and the 0 output

of SS2 (low) activates G8 which activates

5-135. Also, during the 70 msec low- output

G9, generating AIRES-S (waveform E, figure

time of DLI, S c h m i t t trigger ST1 is activated.

10). FF1 remains reset until SS3 resets which

The output of ST1 (waveform B, figure 9)

activates G5 presetting FFl.

activates gate G2 which activates gate G3.

The output of G3 triggers single shot SS1

5 - 1 3 8 . When any select cycle, DDT or

a n d the 0 output of SS1 disables G2 which

interrupt, is being conducted by the Bus

disables G3. The 1 output of SS1 (wave-

Controller service request select and inter-

form C, figure 9), after 2.5 nmsec, triggers

rupt circuit, S11P-P and PCDI-P are gener-

single shot SS2 and the 0 output of SS1

ated and routed to the Bus Controller

activates G2 which activates G3, triggering

alarm and INFIBUS timing circuit.

SS1 once again. The 1 output of SS2 (wave

S11P-P is used for setting a 2 usec time

form D, figure 9) triggers single shot SS3

limit for the function to be selected and

which activates gate G5 which presets

PCDI-P causes the precedence pulse,

flip-flop FF1. SS1 again resets in 2 5

PCDB-P to be generated. With the selection

msec which retriggers SS2. The output of

in progress, S11P-P (waveform, A, figure 11)

SS2 then retriggers SS3. The cycle of

retriggering S S 3 o c c u r s 2 8 t i m e s w i t h i n t h e

msec

time

delay

DLl.

The SS3 1 out-

5-22