CPU level 1 self-interrupt

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 3967-464-0010

with the following exceptions: G2 Is acti-

data (device number) on the INFIBUS for the

vated and 4-bit latch U43 generates RPLS-P,

CPU. The CPU processes the data and gen-

G23 is activated which activates gates G37,

erates the mask bits (waveform S, figure 7).

in this case the level 4 interrupt was ser-

G39, and G40, and G37 activates G27 which

viced and now level 3 is to be opened with

generates PCDI-P. NNTS-P is generated by

interrupt level flip-flops U65 and routed to

the other levels closed. Mask bits LB15-P,

the Bus Controller alarm and INFIBUS timing

LB13-P, and LB12-P are generated by the

circuit and ILOR-N and ILIR-N are generated

CPU presenting them to the mask flip-flops

and routed to the CPU representing a level 4

U71. The CPU then generates STAT-N (wave-

form T, figure 7) which is inverted by in-

internal interrupt. No select signal (SELI-N

through SEL4-N) is generated because the

verter 14. The output of 14 triggers the mask

interrupt is being generated internally by

flip-flops U71. The mask flip-flops U71

the Bus Controller.

are loaded with the mask bits and now Gl,

G4, G11, G13 and G16 are disabled and G6

5-129. The CPU level 1 self-interrupt

is enabled to be activated by a level 3

(DN3R-N) operates in the same manner as a

interrupt request (SRL3-N) . The level 1, 2

CPU level 4 self-interrupt except, G16 is

and 3 interrupt requests (SRLl-N, SRL2-N

activated. The output of G16 activates

and SRL3-N) are cycled in the same manner

G17 and 4-bit latch U52 generates REXS-P

as the level 4 interrupt when the associated

which activates G36. The output of G36

level is opened. The associated select

activates G37 and interrupt level flip-flops

signal, SELl-N, SEL2-N, or SEL3-N, will

U65 generate NNTS-P (high), ILOR-N (high)

be generated and the interrupt level code,

and ILIR-N (high) which are routed to the

a combination of ILOR-N and ILIR-N, repre-

CPU and represent a level 1 self-interrupt.

senting the level of interrupt being cycled

will be coupled to the CPU. The mask flip-

5-130. If two levels of interrupts are re-

flops U71 will be loaded after every cycle,

quested simultaneously, only the interrupt

opening up the next lower priority level of

level which is enabled by the set mask flip-

interrupt. After the level 1 interrupt,

flop U71 is serviced. The same level of

SRLl-N request, level 4 will be opened with

interrupts cannot be serviced successively

the other levels closed.

because, after the first is cycled, mask

flip-flops U71 close that level until all

5-127. When the CPU requests to be se-

other interrupt levels are cycled. When an

lected for transferring the stored program

interrupt and a DDT request (SRLD-N) are

data, the CPU generates SRLC-N, the

requested simultaneously, the high priority

lowest priority transfer request. SRLC-N

DDT request will be serviced first. For

is inverted by inverter 13 which activates

example, if SRL4-N and SRLDLN are re-

gate G15. The output of G15 is applied to

ceived, 4-bit latch U43 generates RLDS-P.

the 2D4 input of 4-bit latch U52 and also

RLDS-P is inverted by I6 which disables

activates gate G9. The output of G9 triggers

G23. The output of I6 activates G22, gen-

4-bit latches U43 and U52 and the cycle is

erating SELD-N, which selects the Processor

repeated as explained previously except that

function requesting INFIBUS access. When

4-bit latch U52 generates RLCS-P. G38 is

the DDT is completed, RL4S-P is generated

activated by RLCS-P which enables gate

again by 4-bit latch U43 and G25 is activated

G35.

which activates G24. The output of G24,

SEL4-N, selects the Processor function re-

5-128. When the Bus Controller alarm and

questing a level 4 interrupt INFIBUS access.

INFIBUS timing circuit generates a CPU

l e v e l 4 internal interrupts, D N U M - P is

5 - 1 3 1 . If master inhibit, MINH-N, is gen-

generated.

If the level 4 interrupt is

erated by the Program Maintenance Panel,

e n a b l e d by the mask flip-flops U71,

G18 will be disabled. With any interrupts

D R U M - P activates gate Gl and the inter-

received, NEXT-N is not generated and the

r u p t cycle is repeated as e x p l a i n e d f o r

the other levels of interrupts

interrupts will not be cycled.

5-21