BUS CONTROLLER A1A3A5 SERVICE REQUEST SELECTION AND INTERRUPT CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

puts of 4-bit latch and U52 also goes high

PCDI-P (waveform D, figure 7). PCDI-P

activating G10 which generates S11P-P.

generates the precedence pulse PCDA-P

Which is routed to the INFIBUS.

S11P-P enables G20 and RL4S-P activates

G25 which enables gate G24 and activates

gates G26, G39, and G40. The output

5-122. The Processor master requesting

the DDT receives SELD-N and the preced-

of G26 disables G28, G30, G32, G36, and

ence pulse and then responds with SACK-N.

G38. G39 and G40 generate low outputs to

interrupt level flip-flops U65 and activate

The Bus Controller alarm and INFIBUS tim-

gate G41. The high output of G41 is applied

ing circuit' then generates RSAK-P (wave-

to interrupt level flip-flops U65 and enables

form E, figure 7) which is inverted by in-

gate G44. Inverter I9 inverts the output of

verter I1. The output of I1, NSAK-N (wave-

G41, causing CYST-N (waveform M, figure 7)

form F, figure 7), is routed to the Bus

to go low which is routed to the Bus Control-

Controller. alarm and INFIBUS timing circuit.

NSAK-N also disables G3 and G21. G3 dis-

ler alarm and INFIBUS timing circuit. At the

ables G9 and G21 disables G22 which causes

same time, delay DLl delays S11P-P for

20 nsec which then activates G20. 15 in-

SELD-N to return to high. The high output of

verts the output of G20 which activates G21.

G9 clears 4-bit latches U43 and U52, caus-

The output of G21 activates G24 which gen-

ing RLDS-P to return to low. The Processor

erates SEL4-N (waveform L, figure 7). The

master then removes SRLD-N and SACK-N.

output of G24 also activates G27 which gen-

RSAK-P goes low and is inverted by I1 which

erates PCDI-P (waveform K, figure 7).

enables G3 again. The Processor master

selected transfers data on the INFIBUS and

how another Processor master may request

5-125. The Processor function, generating

INFIBUS access but will not be serviced

the level 4 interrupt, receives SEL4-N and

until the selected function completes the

the precedence pulse which causes SACK-N

data transfer.

to go low. The Bus Controller alarm and

INFIBUS timing circuit then generates RSAK-P

5-123. When a Processor function requests

(waveform N, figure 7). RSAK-P activates

a level 4 interrupt, it generates SRL4-N .

G44 which generates SCLK-P (waveform 0,

SRL4-N (waveform G, figure 7) from the

figure 7) which is routed to the Bus Control-

INFIBUS activates G4 which enables G5 and

ler alarm and INFIBUS timing circuit, and

activates gate G8. The output of G8 acti-

triggers interrupt level flip-flops U65.

vates gate G18 which generates NEXT-N

Interrupt level flip-flops U65 generate

(waveform I-I, figure 7) which is routed to

ILOR-N and ILIR-N, a level four interrupt

the CPU. When the CPU is ready to accept

binary code, to the CPU, and INTR-N

the interrupt, the CPU generates SCM3-N

(waveform P, figure 7) to the Bus Controller

(waveform I, figure 7) which presets FF3

alarm and INFIBUS timing circuit. INTR-N

and activates G42. The 1 output of FF3

activates G43 and G19. The output of G43,

(high) disables G19 and G43. Disabled G19

RNIR-P (waveform Q, figure 7), is routed to

enables G2, G7, G14, G12, G17 and activates

the Bus Controller alarm and INFIBUS timing

G5. Disabled G43 causes RNIR-P (wave-

circuit and 18. 18 inverts RNIR-P, gener-

form Q, figure 7) to go low and I8 causes

ating INAR-N (waveform R, figure 7), which

INAR-N (waveform R, figure 7) to go high.

is also routed to the Bus Controller alarm

The output of G42, SCRS-N (waveform J,

and INFIBUS timing circuit. The output of

figure 7), is routed to the Bus Controller

G19 disables gates G2, G5, G7, G12, G14

alarm and INFIBUS timing circuit. SCRS-N

and G17. G9 is disabled and 4-bit latches

also clears the interrupt level flip-flops

U43 and U52 are cleared. G21 is disabled

U65.

by the output of 11 which disables G.24.

Disabling G24 causes SEL4-N to return to

5-124. The output of G5 is applied to the

high.

1Dl input of 4-bit latch U43 and activates

G-3. The output of G9 triggers 4-bit latches

5 - 1 2 6 . The Processor function requesting

U43 and U52 which causes the 05 output to

the level 4 interrupt removes its request,

go high and the O1 output of 4-bit latch U43

SRL4-N (returns to high), and places its

to go high, generating RL4S-P. The 05 out-

5-20