BUS CONTROLLER A1A3A5 SERVICE REQUEST SELECTION AND INTERRUPT CIRCUIT.

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

lowest priority to highest, used by Processor

circuit, INFIBUS access circuit, data input

functions to transfer data under CPU control.

and selector circuit, data output and control

status circuit. The TTY Controller, Modem

5 - 1 2 0 . Detail Analysis (see figure 6).

Controller 1, Printer Controller, and Modem

After power is applied to the Processor,

Controller 2 functions operate in a similar

RSET-N is received from the Bus Controller

manner. Therefore, the discussions sup-

alarm and INFIBUS timing circuit which

porting these functions have been combined

clears flip-flop FF3 and mask flip-flops

under the Serial I/O control group heading.

U71 (flip-flop FF2 shown typical). This

The Serial I/O control group functions con-

enables gates Gl, G4, G6, G11, G13 and

sist of the address recognition circuit,

G16. RSET-N also activates gate G42 which

INFIBUS access circuit, clock generator

generates SCRS-N which is routed to the Bus

circuit, control register circuit, data selec-

Controller alarm and INFIBUS timing circuit.

tor control circuit, and asynchronous data

SCRS-N also resets the interrupt level flip-

transfer control circuit. The Mag Tape Con-

flops U65 (flip-flop FF2 shown typical).

troller function consists of the address

The 1 output of FF3 (low) activates gates

recognition circuit, INFIBUS access circuit,

G19 and G43. The output of G19 disables

data input and selector circuit, data output

gates G2, G5, G7, G12, G14 and G17.

and control register circuit, and read/write

The output of G43, RNIR-P, is routed to the

control status circuit. The I/O Controller

Bus Controller alarm and INFIBUS timing

function consists of the clock circuit,

c i r c u i t . RNIR-P is also inverted by inverter

address recognition, done and reset circuit,

I8, generating INAR-N which is routed to

data circuit, interface circuit, and INFIBUS

the Bus Controller alarm and INFIBUS tim-

access circuit. The Program Maintenance

ing circuit.

Panel function consists of the address/data

switch identification, multiplexers, and

5 - 1 2 1 . When a Processor master module is

LED circuit, CPU register selection circuit,

requesting a DDT, SRLD-N (highest priority)

address multiplexer, bus driver receiver,

is generated on the INFIBUS. SRLD-N (wave-

and recognition circuit, data multiplexer

form A, figure 7) is received by the Bus

and bus driver receiver circuit, switch flip-

Controller service request selection and

flops and single action discriminator circuit,

interrupt circuit and inverter I2 inverts

miscellaneous control circuit, state gener-

SRLD-N activating gate G3. The output of

ation and micro-operations circuit, and

G3 is routed to the 1D3 input of the 4-bit

INFIBUS access circuit.

latch U43 and activates gate G9 which trig-

gers 4-bit latches U43 and U52. The 4-bit

BUS CONTROLLER A1A3A5 SERVICE

5-118.

latches U43 and US2 activate gate G10

REQUEST SELECTION AND INTER-

which generates S11P-P (waveform B, figure

RUPT CIRCUIT.

7) The 4-bit latch U43 also generates

5 - 1 1 9 . General. The Bus Controller ser-

RLDS-P. Inverter 16 inverts RLDS-P which

enables gate G22. The output of I6 also

vice request selection and interrupt circuit

allocates INFIBUS time to Processor func-

disables gates G23 and G25 and activates

gate G26. The output of G26 disables

tions for information transfers on a priority

gates G28, G30, G32, G36, and G38. At

b a s i s . It receives and services two direct

the same time, S11P-P enables gate G20

data transfer (DDT) requests a and four levels

of Interrupt requests. The lowest priority is

and delay DLl delays S11P-P by 20 nsec.

After the 20 nsec delay, G20) is activated

the DDT request used by the CPU to trans-

fer the stored software programs and data.

and its output is inverted by inverter I5

The highest priority is the DDT request used

which activates gate G21. The output of

G21 activates G22 which generates SELD-N

by Processor masters to transfer data direct-

(waveform C, figure 7). The output of G22

ly to and from Processor functions. In

also activates gate G27 which generates

between are the level 1 through 4 Interrupts,

5-19