CLEAR/WRITE MODE

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

the selected CM BSM. 50 nsec after AIX-P

5-110. With asynchronous cycle reinitiate,

is generated MEM AVAIL-P goes low to

the control signals may assume their appro-

notify the Processor Core Memory Control-

priate values prior to the end of a cycle in

ler that the Core Memory is busy. RDR-P

progress. The next cycle is then auto-

is now generated which clears the data reg-

matically initiated by the Core Memory

i s t e r . The timing and control logic circuits

when MEM AVAIL-P returns to logic 1.

now generate PRE YRT-P and MRT-P which

cause the control and buffer logic circuits

5 - 1 1 1 . In the clear/write mode zone con-

to generate XRTl-P, XRT2-N, and YRT-N.

trol signals, ZW1-P and ZW2-P, cause

This causes the address decoding and

byte operation of the Core Memory. In

switching circuits and X and Y current

the clear/write mode, if both ZW1-P and

sources to generate the appropriate X read

ZW2-P are logic 1, clear/write mode is

currents, XCA0-P through XCA7-P and

performed on the word. In the clear/

XSOO-P through XS15-P, and Y read currents,

write mode, if ZWl-P is logic 1 and

YCAO-P through YCA7-P and YS00-N through

ZW2-P is logic 0, a clear/write oper-

YS07-N, as determined by MAR00-P through

ation is performed on byte 1 (DI00-P

MAR12-P. The X read currents cause cur-

through DI08-P) and 1 read/restore

rent flow through one of the 128 X lines

operation is performed on byte 2

from the X diode matrix and the Y read cur-

(DI09-P through DI17-P). In the

rents cause current flow through one of the

clear/write mode, if ZWl-P is logic 0

64 Y lines from the Y diode matrix. At the

and ZW2-P is logic 1, a read/restore

cores where these lines intersect, if a one

operation is performed on byte 1 and a

was stored, core turnover occurs. Where a

clear/write operation is performed on

core turnover occurs a pulse is coupled to

byte 2.

the appropriate sense line, S-00 through

S-17, however, because the sense ampli-

5 - 1 1 2 . The two functional modes of

fiers are not enabled by SAS-P this data is

the Core Memory are described in the

not strobed through the sense amplifiers.

following paragraphs.

This clears the selected address within the

core memory stack. The write portion of

5 - 1 1 3 . CLEAR/WRITE MODE. The

the cycle begins as the Processor Core

clear/write mode is used to store data

Memory Controller data input signals,

into the core memory stack without

DI00-P through DI17-P, are clocked into

refererce to the data already stored in

the data register by timing and control logic

the selected address. The core memory

signal DIX-P; Data inhibit signals DATA

stack location is first cleared then the

INH00-P through DATA INH17-P, from the

new data is written in. The clear portion

data register are strobed through the inhibit

is a read cycle but the data is not read

drivers by TINH-P. The inhibit drivers gen-

out. T h e cycle initiated by the Proces-

erate the inhibit signals, INH00-N through

sor Core Memory Controller signal WT

INH17-N, wherever a logic 0 is to be stored

INIT-P going to logic 1 with the following

in the core memory stack. Controlled by

conditions; RD INIT-P at logic 0, RD ONLY-P

timing and control logic signal MWT-P,

at logic 0, and FULL CYC-P at logic 1.

control and buffer logic circuit generates

Under these conditions, AIX-P is generated

signals WT1-P and WT2-P. This causes

which clocks address bits AI00-P through

the address decoding and switching circuits

AI15-P from the Processor Core Memory

and X and Y current sources to generate the

Controller into the address registers 00

appropriate X write currents, XCC0-N

through 15. The outputs of address reg-

through XCC7-N and XS00-P and XS15-P,

isters 00 through 12, MAR00-P through

and Y write currents, YCC0-N through

MAR12-P, are applied to the address de-

YCC7-N and YS00-P and YS07-P, a:; detcr-

coding and switching circuits. Address bits

mined by MAR00-P through MAR12-P. When

AI13-P, AI14-P, and AI15-P are decoded by

the data is written into the selected address,

the address registers 13, 14, and 15. The

MEM AVAIL-P returns to logic 1 indicating

outputs of the address registers 13, 14,

to the Processor Core Memory Controller

and 15, BSM00-P through BSM03-P, enable

that a new cycle may be initiated.

5-17