CORE MEMORY FUNCTIONAL BLOCK DIAGRAM DESCRIPTION.

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

function notifies Modem Controller 2 that

5-106. CORE MEMORY FUNCTIONAL

BLOCK DIAGRAM DESCRIPTION.

data is to be transferred, a programmed

data transfer (PDT) status bit is set in the

5-107. GENERAL. The following paragraphs

status register. When the CPU detects the

PDT status bit, the CPU jumps to a sub-

contain a functional block diagram discussion

of the Core Memory (figure 5). The Switch

routine which determines whether a write or

read operation is to be performed. If a

Group Core Memory contains 8 Core Mem-

ory Basic Storage Modules (CM BSM) and the

write operation is to be performed by the

ACOC Core Memory contains 8. CM BSM's,

CPU, the CPU places the data register

address on the INFIBUS address lines,

therefore, this discussion will discuss a

system with one CM BSM, unless applicable.

places the data on the INFIBUS data lines,

and generates RITE-N. The data is loaded

into Modem Controller 2 which then gener-

ates DONE-N to free the INFIBUS. Mode:.,

5-108. The Core Memory can operate in four

Controller 2 now converts the parallel input

modes: clear/write, read/restore, read/

data from the INFIBUS to serial data that is

m o d i f y / w r i t e , and read only. However, only

clocked to the VF Comm Link 2 function. If

the clear/write and read/restore modes are

a read operation is to be performed, the CPU

functional. The read/modify/write mode is

places only the data register address on the

not functional because FULL CYC-P is

INFIBUS address lines and the serial data

always 5 volts. T h e r e a d o n l y m o d e i s n o t

from the VF Comm Link 2 function which has

functional because RD ONLY-P is always

been converted to an 8-bit parallel byte is

In the clear/write mode all of the

0 volts.

strobed to the INFIBUS data lines. The

cores at the selected address are cleared

Modem Controller 2 then generates DONE-N

(returned to logic 0) and any data generated

to free the INFIBUS.

is not read out of the Core Memory. in

the read-restore mode the data is read out

5-103. If the level 2 interrupt is enabled

of the selected address and the same data is

returned to that address. In the read/modify/

by the control word in the control register,

write mode the data is read out of the

whenever the PDT status bit is set, a level

2 interrupt is generated, as explained pre-

selected address and new or revised data is

viously. The CPU then addresses the data

placed into that address of the Core Memory.

In the read only mode the data is read out

ation in the same manner as when the level

of the selected a d d r e s s a n d t h a t a d d r e s s i s

2 interrupt was disabled.

left cleared. The read only mode is not func-

tional in the Core Memory because RD

ONLY-P is tied to logic 0 in the Processor

Modem Controller 2 operates at

5-104.

Core Memory Controller. The clear/write

1200 baud which is derived from the clock

and read/restore modes are known as full

signal, CLKA-N, from the INFIBUS.

cycle modes, The read/modify/write mode

is known as a split cycle because of the tlm-

5-105. PROGRAM MAINTENANCE PANEL.

ing pause before instructions are received by

The Program Maintenance Panel function

the Core Memory to per form the write operation.

Each of the two functional modes may use

enables an operator to manually enter ad-

dress, data, and control inputs to the

either synchronous or a asynchronous cycle

Processor. It allows the operator to read

reinitiate.

from or write into (DDT) any addressable

area of the Processor and usually operates

as a master. It can also, under control of

5-109. With synchronous cycle reinitiate,

the stored software program, display on the

signal RD INIT-P or WT INIT-P from the

front panel various steps within the program

Processor Core Memory Controller to the

(operates as a slave). The Program Main-

CM MIA timing and control logic circuits

tenance Panel also generates a level 1

is returned to logic 0 before the end of the

interrupt when the attention (attn) switch

c y c l e . To initiate the next cycle, RD:

located on the front panel is depressed.

INIT-P or WT INIT-P goes to logic 1.

5-16