MODEM CONTROLLER 1

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

viously. The CPU then addresses the data

5-78. Under control of the CPU, Modem

Controller 1 is enabled to generate or

ation in the same manner as when the level

prevented from generating a level 2 inter-

2 interrupt was disabled.

rupt whenever data is to be transferred by

Modem Controller 1. The control word that

has been loaded into the control register

5 - 7 4 . The baud rate of the TTY Controller

enables or disables Modem Controller 1

is controlled by a signal from the TTY func-

INFIBUS access circuits which generate the

tion which is derived from the line frequency

level 2 interrupt. If the level 2 interrupt is

Therefore, if the line frequency varies which

disabled by the control word, the CPU

in turn varies the speed of the TTY motor,

regularly checks status (reads status reg-

the baud rate varies proportionately.

ister) to determine whether a data transfer

is to be performed. When the VF Comm Link

1 function notifies Modem Controller 1 that

5 - 7 5 . MODEM CONTROLLER 1. The Modem

data is to be transferred, a programmed data

Controller 1 function receives 8-bit bytes of

transfer (PDT) status bit is set in the status

data from the INFIBUS and converts these

bytes to serial words that are routed to the

status bit, the CPU jumps to a subroutine

VF Comm Link 1 function. It also receives

which determines whether a write or read

serial words from the VF Comm Link 1 func-

operation is to be performed,. If a write

tion and converts the words to 8-bit bytes

operation is to be performed by the CPU,

of data that are placed on the INFIBUS.

the CPU places the data register address on

Modem Controller 1 is a slave that gener-

the INFIBUS address lines, places the data

ates a level 2 interrupt and is assigned

on the INFIBUS data lines, and generates

address F93X 16. There are three registers

RITE-N. The data is loaded into the Modem

located in Modem Controller 1; the data

Controller 1 which then generates DONE-N

r e g i s t e r , control register, and status reg-

to free the INFIBUS. Modem Controller 1

i s t e r . Each register is assigned a separate

now converts the parallel input data from

address which allows the stored software

the INFIBUS to serial data that is clocked

program to write into or read from each reg-

to the VF Comm Link 1 function. If a read

ister as determined by the level of RITE-N.

operation is to be performed, the CPU places

The data register is assigned address

only the data register address on the INFI-

F938 16. The control register address is

BUS address lines and the serial data from

F936 16, and the status register is F930 16.

the VF Comm Link 1 function which has been

converted to an 8-bit parallel byte is strobed

5-76. If the stored software program is to

to the INFIBUS data lines. The Modem

clear Modem Controller 1, F930 16 is placed

Controller 1 then generates DONE-N to

on the INFIBUS address lines, ABOO-N

free the INFIBUS.

through AB15-N and no data is placed on

the INFIBUS data lines, DBOO-N through

5-79. If the level 2 interrupt is enabled by

DB15-N, and a write operation (RITE-N low)

the control word in the control register,

is performed. This write operation to the

whenever the PDT status bit is set, a level

status register clears Modem Controller 1.

2 interrupt is generated, as explained pre-

Modem Controller 1 then generates DONE-N

viously. The CPU then addresses the data

which frees the INFIBUS.

ation in the same manner as when the level

2 interrupt was disabled.

5-77. The stored software program can also

read from or write into the control register,

5 - 8 0 . Modem Controller 1 operates at 1200

as determined by the level of RITE-N, by

baud which is derived from the clock signal,

placing the control register address on

CLKA-N, from the INFIBUS.

the INFIBUS address lines. After the con-

trol register is written into or read from,

5 - 8 1 . BLOCK TRANSFER ADAPTER. The

Modem Controller 1 generates DONE-N

Block Transfer Adapter is a master which

which frees the INFIBUS.

5-12