TTY CONTROLLER

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

T h e T T Y C o n t r o l l e r t h e n g e n e r a t e s DONE-N

s data lines, and generates RITE-N.

which frees the INFIBUS.

The data is loaded into the Parallel I/O

which then generates DONE-N to free the

5 - 7 1 . The stored software program can also

INFIBUS. The Parallel I/O now clocks the

read from or write into the control register,

input data from the INFIBUS to the Alarm

as determined by the level of RITE-N.. by

Control and VF Comm Link 1 function. If a

placing the control register address on the

read operation is to be performed by the

INFIBUS address lines. After the control

CPU, the CPU places only the data register

address on the INFIBUS address lines and

TTY Controller generates DONE-N which

the parallel data from the Alarm Control and

frees the INFIBUS.

VF Comm Link 1 function which is now loaded

into the Parallel I/O is strobed to the INFIBUS

Under control of the CPU, the TTY

data lines. The Parallel I/O then generates

5-72.

DONE-N to free the INFIBUS.

Controller is enabled to generate or pre-

vented from generating a level 2 interrupt

5-68.

whenever data is to be transferred by the

If the level 1 Interrupt IS enabled by

TTY Controller. T h e c o n t r o l w o r d t h a t h a s

the control word in the control register,

been loaded into the control register enables

whenever the PDT status bit is set, a level

or disables the TTY Controller INFIBUS

1 interrupt I S g e n e r a t e d , a s e x p l a i n e d p r e -

access circuits which generate the level 2

v i o u s l y . The CPU then addresses the data

Interrupt. If the level 2 interrupt is dis-

abled by the control word, the CPU regu-

ation in the same manner as when the level

1 Interrupt was disabled.

larly checks status (reads status register) to

determine whether a data transfer is to be

5-69.

performed. When the TTY function notifies

TTY CONTROLLER. The TTY Con-

the TTY Controller that data is to be trans-

troller function receives 8-bit bytes of data

ferred, a programmed data transfer (PDT)

from the INFIBUS and converts these bytes

s t a t u s b i t i s s e t i n t h e s t a t u s register.

to 11-bit, ASCII coded, serial words that

W h e n t h e C P U d e t e c t s t h e P D T s t a t u s bit,

are routed to the TTY function. I t a l s o r e -

ceives: 11-bit, ASCII coded, serial words

the CPU lumps to a subroutine which deter-

from the TTY function and converts these

mines whether a write or read operation is

words to 8-bit bytes of data that are placed

t o b e p e r f o r m e d . If a write operation is to

be performed by the CPU, the CPU places

o r t h e I N F I B U S . The TTY Controller is a

the data register address on the INFIBUS

slave that generates a level 2 interrupt and

address lines, places the data on the

is assigned address F8OX 16. There are

three registers located in the TTY Controller;

INFIBUS data lines, and generates RITE-N.

the data register, control register, and

The data is loaded into the\TTY Controller

status register. Each register is assigned

which then generates DONE-N to free the

INFIBUS. T h e T T Y C o n t r o l l e r n o w c o n v e r t s

a separate address which allows the stored

software program to write into or read from

the parallel input data from the INFIBUS to

serial data that is clocked to the TTY func-

each register as determined by the level of

RITE-n;. T h e d a t a r e g i s t e r i s a s s i g n e d

t i o n . If a read operation is to be performed,

a d d r e s s F808 16. T h e c o n t r o l r e g i s t e r

the CPU places only the data register

address is F806 16 and the status register is

address on the INFIBUS address lines and

F800 16.

the serial data from the TTY function which

has been converted to an 8-bit parallel byte

is strobed to the INFIBUS data lines. Then

the TTY Controller generates DONE-N to

free the INFIBUS.

5-73. If the level 2 interrupt IS enabled by

the control word in the control register,

whenever the PDT status bit is set, a level

2 interrupt is generated, as explained pre-

5-11