PARALLEL I/O

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

lines. When the Autoload senses its address

assigned address F92X 16. There are three

registers located in the Parallel I/O; the

on the INFIBUS lines, the first ROM data

word is placed on the data lines. The CPU

data register, control register, and status

reads this data then addresses the Autoload

function again and increases the Autoload

arate address which allows the stored soft-

address by two to FB02 16. This occurs

ware program to write into or read from each

eight times and each time a new ROM data

word is read by the CPU and placed in the

The data register is assigned address F928 16.

Core Memory. The CPU then uses these

The control register address is F926 16, and

eight data words to initialize the Mag Tape

the Status register is F920 16.

Controller and Block Transfer Adapter. The

Mag Tape Controller and Block Transfer

5-65. If the stored software program is to

Adapter then load the operating program or

clear the Parallel I/O, F920 16 is placed on

utility print program into a buffer area in

the INFIBUS address lines, AB00-N through

the Core Memory. When the entire program

AB15-N. Also, no data is placed on the

is loaded into the buffer area, the Autoload

INFIBUS data lines, DB00-N through DB15-N,

function is again addressed and the Autoload

and a write operation (RITE-N low) is per-

ROM program is read by the CPU. The pro-

formed. This write operation to the status

gram stored in the buffer area of the Core

Memory is then transferred to the proper

lel I/O then generates DONE-N which frees

location in Core Memory. The last data

the INFIBUS.

word of the program will cause the Processor

to either halt or execute the last instruction

5-66. The stored software program can also

of the program which may cause the CPU to

read from or write into the control register,

jump to the beginning of the operating pro-

as determined by the level of RITE-N, by

gram.

placing the control register address on the

INFIBUS address lines. After the control

5 - 6 3 . PARALLEL I/O. The Parallel I/O func-

tion receives 12-bit words of data from the

Parallel I/O generates DONE-N which frees

INFIBUS and couples These data bytes and

the INFIBUS.

control signals to the Alarm Control and VF

Comm Link function. It also receives 12-bit

5-67. Under control of the CPU, the Paral-

data words and control signals from the

lel I/O is enabled to generate or prevented

Alarm Control and VF Comm Link function

from generating a level 1 interrupt whenever

and couples these data bytes to the INFI-

data is to be transferred by the Parallel I/O.

BUS. The Parallel I/O receives data under

The control word that has been loaded into

control of the stored software program that

the control register enables or disables the

controls various lamps on the Alarm Panel. It

Parallel I/O INFIBUS access circuits which

also receives various alarm conditions from

generate the level 1 interrupt. If the level

the Alarm Control and VF Comm Link function.

1 interrupt is disabled by the control word,

These alarms are used to notify the Processor

the CPU regularly checks status (reads

of external failures such as blown fuses,

status register) to determine whether a data

mag tape not ready and executive program

transfer is to be performed. When the Alarm

alarm. The Parallel I/O also enables the

Control and VF Comm Link function notifies

Alarm Control and VF Comm Link function,

the Parallel I/O that data is to be trans-

under stored software program control, to

ferred, a programmed data transfer (PDT)

output a phone number, and, when the call

status bit is set in the status register.

is answered cuts the VF Comm Link 1 func-

When the CPU detects the PDT status bit,

tion into the communications link. In the

the CPU jumps to a subroutine which deter-

ACOC group, the Parallel I/O can cut either

mines whether a write or read operation is

the VF Comm Link 1 or VI' Comm Link 2 into

to be performed. If a write operation is to

the communications link.

be performed by the CPU, the CPU places

the data register address on the INFIBUS

5 - 6 4 . The Parallel I/O function is a slave

address lines, places the data on the

that generates a level 1 interrupt and is

5-10