AUTOLOAD

T.O. 31S5-4-308-l

TM11-5805-663-14-13

NAVELEX 0967-464-0010

requested (RITE-N high) and the page num-

addresses. The Core Memory Controller

ber is presented on the INFIBUS data lines

can only be slaved by other master Proces-

to be read by the requesting function.

sor functions and cannot request access to

the INFIBUS.

5-59. AUTOLOAD. The Autoload function

is a masterthat contains a fixed, stored

5 - 5 7 . The Core Memory Controller is as-

instruction set (ROM program) which is

signed addresses 0000 16 through EFFF 16

used to control loading of the operating

for storing the system software program and

program or utility print program (UPP) in the

data. Address 0000 16 through 00FF 16 are

Core Memory. The Autoload function can

known as the executive space of the Core

perform direct data transfers on the INFIBUS

Memory. Whenever an address from 0000 16

and can also generate a level 1 interrupt

request for INFIBUS access.

through BFFF 16 is detected on the INFIBUS

by the Core Memory Controller, and a read

5-60. The Autoload function is initiated

or write operation is performed at the selec-

when the INFIBUS Autoload, ATLD-N, line

ted Core Memory Address, Addresses

is activated. ATLD-N is generated by the

C000 16 through DFFF 16 are used to trans-

Bus Controller after power turn on; if enabled

fer data in or out of areas in the Core

as discussed previously or by the operator

Memory referred to as pages. There are 16

pressing the lighted load switch on the

pages that may be assigned for use in the

front panel. When the operator presses the

Core Memory (only two used) and the same

reset switch on the front panel, the Program

address range is used for all 16 pages. To

Maintenance Panel generates REPB-N which

determine which page data is to be transferred

causes the Bus Controller to generate

to or from the Core Memory Controller must

master reset, MRES-N. MRES-N clears all

be first set at the particular page number.

Processor functions and causes the load

Whenever a page address is sensed on the

switch located on the front panel to light.

INFIBUS by the Core Memory Controller, the

The operator must load a program tape on a

Core Memory Address is shifted to the

Mag Tape Unit and then with the lighted

right (divided by two) by dropping the least

load switch depressed the Program Main-

significant bit and the page number (0 or 1)

tenance Panel generates ATLD-N which is

is inserted in the most significant bit.

sensed by the Autoload function.

5 - 5 8 . To read or write into a page of Core

5 - 6 1 . The Autoload function, after sensing

Memory, the master first places FFFF 16 on

ATLD-N, performs a DDT as explained pre-

the INFIBUS address lines and the selected

viously. During this DDT, the address

page number, 0000 16 through 000F l6, on

0005 16 is placed on the address lines,

AB00-N through AB15-N, the Autoload

the data lines with the RITE-N line low for

a write operation. The Core Memory Con-

address, FB00 16, is placed on the data

lines, DB00-N through DB15-N, and RITE-N

troller senses this and the page number is

written into in an Internal register when

is generated. This causes the Autoload

STRB-B is generated by the master. Now

address to be stored in the Core Memory.

when the page addresses are used they will

The Core Memory Controller then indicates

be modified by having the most significant

the data is stored in the Core Memory by

four bits replaced with the stored page num-

generating DONE-N which causes the Auto-

ber and then presented to the Core Memory to

load to free the INFIBUS by removing STRB-N.

transfer data into or out of the page. To

transfer data out of or into another page,

5 - 6 2 . After the DDT, the Autoload function

the cycle of selecting the page must be

initiates a level 1 interrupt by generating

repeated to set the Core Memory Controller

SRLl-N. The level 1 interrupt IS performed

internal register. To determine which page

as explained previously. The CPU then

the Core Memory Controller has been pre-

grants the Autoload function INFIBUS access

viously set at, the Internal register is

by placing the Autoload address (stored in

addressed, FFFF 16, with a read operation

Core Memory during DDT) on the address

5-9