CORE MEMORY CONTROLLER

T:O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

attention (attn) switch on the front panel IS

Controller whenever the reset switch lo-

depressed. This causes the Bus Controller

cated on the front panel is depressed.

to generate a level 1 internal inter-

REPB-N causes the Bus Controller to gener-

ate MRCS-N (master reset) which clears all

rupts to inform the CPU of a request

Processor functions with the exception

by an operator for INFIBUS access.

Not used in TCDS.

the CPU.

5 - 5 3 . CPU. The central processor unit

(CPU) executes the software program stored

5-49 The power fall, power restart, and

in the Core Memory and processes data

software clock (LFRQ-N) level 4 internal

interrupts have the same priority level as

that is stored in the Core Memory or re-

the Processor level 4 interrupt (second

ceived from other Processor functions. It

priority).

also routes data to or from other Processor

When the Bus Controller senses one of these

functions and Core Memory, formats data,

inputs, the Bus Controller informs the CPU

and under the control of the stored software

of an interrupt with NEXT-N and the CPU

program controls the operation of the Proc-

r e s p o n d s with SCM3-N as discussed pre-

e s s o r . The CPU operates as a master or a

viously for the Processor system interrupts.

slave and performs internal arithmetic and

If no other DDT's or interrupts are being

logical operations independent of other

requested, the Bus Controller generates

Processor functions which minimizes its

SACK-N (no request-select lines are in-

utilization of the INFIBUS.

volved). As discussed for the level 4

5 - 5 4 . The CPU is connected to the Bus

through level 1 interrupts, the Bus Control-

ler generates HOLD-N and a binary code

Controller through the interconnecting

(ILOR-N and ILlP-N which represents the

module for the handling of Interrupts.

Interrupt level) that are routed to the CPU.

While handling interrupts the CPU performs

The Bus Controller then generates data lines

automatic save and restore of the program

count and status. The interrupting device

DBOO-N through DB02-N which is a 3-bit

number is also) saved prior to the CPU's

device number. A d i f f e r e n t d e v i c e n u m b e r

automatic jump to the prestored interrupt

is generated for each of the three internal

vector location of the interrupting level in

interrupts. As a result the CPU is able to

the Core Memory.

distinguish between the three level 4 inter-

nal interrupts and the level 1 self-interrupt.

5 - 5 5 . When the CPU requires the INFIBUS

for a data transfer it generates a CPU inter-

The Bus Controller then generates

5-50.

rupt (SELC-N is generated) as explained

STRB-N and DNOL-P and removes SACK-N.

previously. The CPU also operates as a

The CPU reads the device number generated

slave and recognizes its internal register

by the Bus Controller and then generates

addresses when they are on the INFIBUS.

DONE-N to indicate a completion. The Bus

Data can be either written into or read out

Controller then removes STRB-N which frees

of these registers (depending on the level

the INFIBUS. The CPU, under controller of

of RITE-N) by either master Processor func-

the stored software program, jumps tc a

subroutine to handle the internal interrupt

tions.

5 - 5 1 . The Bus Controller generates CLKA--N

5-56.

which is a 25 MHz square wave used by the

Autoload, Modem Controller 1, Block Trans-

fer Adapter, Mag Tape Controller, I/O Con-

troller, Modem Controller 2, and Program

Maintenance Panel functions for timing

purposes.

5 - 5 2 . REPB-N is generated by the Program

Maintenance Panel and routed to the Bus

5-8