BUS CONTROLLER-CONT. - TM-11-5805-663-14-130059

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

The PWST-N input to the Bus Con-

5-46.

5-41.

hen a Processor function requests

operation is the same

troller from the PFD/CLOCK function is the

interrupt,

a level

as a level 4 Interrupt except that SRL2-N

power fail/power restart signal. It is a 9.6

and SEL2-N are used and the Bus Controller

kilohertz square wave signal that is gen-

erated 2.2 to 3.0 msec before loss of reg-

generates a binary code (ILOR-N and IL1R-N)

ulated dc power and it is a level 4 internal

which represents a level 2 interrupt. Also,

interrupts. The Bus Controller, upon

the CPU generates mask bits (LB12-P through

sensing PWST-N, generates an internal

ich block the level 2 interrupt

level 4 internal interrupts to the CPU

to notify it of eventual loss of power

and open the level 1 interrupt.

and then generates master reset pulses

5-42. When a Processor function requests

MRES-N. MRES-N is routed to all

a level 1 Interrupt, operation is the same

Processor functions to clear each

function. Between these MRES-N pulses,

as a level 4 interrupt except that SRL1-N

the CPU performs required operations for an

and SELl-N are used and the Bus Controller

generates a binary code (ILOR-N and IL1R-N)

orderly shutdown. If regulation is only

lost momentarily and then regained, the

which represents a level 1 interrupt. Also,

Bus Controller generates a second level 4

the CPU generates mask bits (LB12-P through

LB15-P) which block the level 1 Interrupt

internal interrupts to notify the CPU

and open the level 4 interrupt.

of restored power. Associated with

power fail and power restart internal

Interrupts are PFIN-N, PRIN-N and

If SACK-N is not sensed by the Bus

5-43.

PRAL-N inputs to the Bus Controller

Controller within 2 usec after SEL4-N,

from the Program. Maintenance Panel.

SEL3-N, SEL2-N o r S E L 1 - N a n d P C D A - P

PFIN-N is generated by a switch behind

the front panel and the Bus Controller uses

is generated, the Bus Controller generates

SACK-?`: which will abort the associated

PFIN-N to inhibit a power fail level

interrupt request. If DONE-N is not gen-

4 internal interrupts. PRIN-N and

erated by the CPU within 2 usec after

PRAL-N are generated by a three

STRB-N is generated by the interrupting

position switch located behind

function, the Bus Controller generates

to inhibit the power restart level 4

QUIT-N which aborts the interrupt and frees

internal interrupts. in the AL

p o s i t i o n , PRAL-N is generated and

the INFIBUS.

the Bus Controller generates auto-

The lowest level priority for INFIBUS

5-44.

load signal, ATLD-N, when power re-

access is CPU selection and service. This

start is indicated instead of the

priority, called CPU interrupt: operates in

level 4 internal interrupts. In the

exactly the same manner as module selec-

OFF position, the level 4 internal

interrupts is enabled and ATLD-N is

tion and service (DDT) except that this

interrupt uses the SRLC-N and SELC-N sig-

inhibited.

nals rather than the SRLD-N and SELD-N

The LFRQ-N input to the Bus Con-

5-47.

s i g n a l s . The CPU interrupt is also a DDT

troller is a pulse generated every 40 msec

however, these transfers occur only between

by the PFD/Clock function. The Bus Con-

the CPU and the Core Memory Controller.

troller uses this pulse to also generate a

They are generated when it is required to

level 4 internal interrputs. Every 40

write data into or read data out of the Core

msec the LFRQ-N level 4 internal

Memory under control of the stored software

interrupts causes the CPU to update

program.

the calendar and clock program stored

in the Core Memory. Associated with

LFRQ-N is the LFIN-N input from

5-45.

the Program Maintenance Panel which is

The secondary function of the Bus

generated by a switch located behind the

Controller is to generate CPU internal

front panel. LFIN-N inhibits the LFRQ-N

interrupts. CPU internal interrupts are

generated by the Bus Controller for

level 4 internal interrupts.

power fail, power restart, to update

The EXAT-N input is generated by

5-48.

the calendar and clock program stored

the Program m Maintenance Pane! when the

in the Core Memory, and for operator

attention.

5-7