BUS CONTROLLER-CONT. - TM-11-5805-663-14-130058

T.O. 31S85-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

figure 4) to be generated. DNOL-P informs

tion of the data transfer, if no other func-

the CPU that the interrupting functions de-

tion is requesting INFIBUS access, STRB-N

vice number is on the INFIBUS. The CPU

is removed and the INFIBUS is idle. If

reads the device number from the INFIBUS

either master does not receive DONE-N

and then generates DONE-N (waveform L,

within 2 usec after STRB-N is generated,

figure 4) to indicate the interrupt request is

the Bus Controller generates QUIT-N which

loaded in the CPU. After the removal of

aborts the service cycle and frees the

DONE-N, the interrupting function removes

INFIBUS for other data transfers by forcing

STRB-N which frees the INFIBUS for other

the selected master to remove STRB-N.

operations.

5-36. When a function requests a level

5-38. Between these other INFIBUS oper-

four interrupt, it generates SRL4-N (wave-

ations, the CPU transfers the device num-

form A, figure 4). The Bus Controller senses

ber of the interrupting function to the level

SRL4-N and generates NEXT-N (waveform B,

4 area of executive space in the Core Mem-

figure 4) to the CPU through the intercon-

ory. The CPU now vectors to a stored soft-

necting module (ICM). NEXT-N informs the

ware program subroutine that accesses the

CPU that an interrupt has been sensed and

interrupting function and allows data to be

the CPU completes its current step and

transferred into or out of the interrupting

jumps to an interrupt stored software pro-

function. The actual sequence of events

gram subroutine. When ready to accept the

involved is determined by the stored soft-

interrupt, the CPU generates SCM3-N (wave-

ware program.

form C, figure 4) to the Bus Controller via

the ICM. SCM3-N allows the Bus Controller

5-39. While the device number is being

to select the interrupt if the higher priority

processed by the CPU, the CPU generates

signal SRLD-N is not being generated by a

mask bits LB12-P through LB15-P (waveform

master. The Bus Controller now generates

M, figure 4) which are routed to the Bus

the select line, SEL4-N (waveform D, fig-

Controller. At the same time the CPU gen-

ure 4), and the precedence pulse, PCDA-P

erates STAT-N (waveform N, figure 4) which

(waveform E, figure 4). The interrupting

strobes the mask bits into the Bus Con-

function senses SEL4-N, traps the proce-

troller. The mask bits are used to block

dence pulse, and then removes SRL4-N and

the serviced interrupt level and allows the

generates SACK-N (waveform F, figure 4).

next lower priority interrupt level to be se-

SACK-N prevents other functions from re-

lected. In this way one interrupt level

questing INFIBUS access and is sensed by

cannot tie up the CPU and the four levels

the Bus Controller which removes SEL4-N .

of interrupts are each sequentially serviced.

The Bus Controller then generates HOLD-N

During a level 4 interrupt INFIBUS access

(waveform G, figure 4) which is routed to the

request, the level 4 interrupt will be closed

CPU. HOLD-N prevents the CPU from per-

(masked) and the level 3 interrupt will be

forming any operations with the Core Mem-

opened. When the level 3 interrupt is com-

ory. The Bus Controller also generates a

pleted the level 2 interrupt will be serviced.

binary code, ILOR-N and IL1R-N (waveform

When the level 2 interrupt is completed,

H, figure 4), which is routed to the CPU.

the level 1 interrupt is serviced and when

This binary code informs the CPU that a

the level 1 interrupt is completed the level

level 4 interrupt has been selected.

4 interrupt is opened again.

5-40. When a Processor function requests

5 - 3 7 . The selected interrupting function

a level 3 interrupt, operation is the same as

now places its device number (waveform 1,

a level 4 interrupt except that SRL3-N and

figure 4) on the INFIBUS data lines DB04-N

SEL3-N are used and the Bus Controller

through DBl-N. It then generates STRB-N

generates a binary code (ILOR-N and IL1R-N)

(waveform J, figure 4) and removes SACK-N

which represents a level 3 interrupt. Also,

which allows a second interrupting function

the CPU generates mask bits (LB12-P through

to be selected. The Bus Controller senses

LB15-P) which block the level 3 interrupt

the generation ofSTRB-N and the removal of

and open the level 2 interrupt.

SACK-N which causes DNOL-P (waveform K,

5-6