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T.O. 31S5-4-308-1
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
Controller generates SACK-N which will
request line is activated by the CPU and
abort the selection cycle. The function
detected by the Bus Controller.
requesting the INFIBUS access must then
reinitiate the request.
5 - 3 2 .  The precedence pulse, PCDA/B-P is
chained through all functions of the Pro-
5-34. After the selected master generates
cessor and determines which function (when
SACK-N, SRLD-N is removed. The Bus Con-
more than ore function is requesting the
troller senses SACK-N and the removal of
INFIBUS on the same priority level) will gain
SRLD-N and then removes SELD-N. The
INFIBUS access first. The precedence pulse
selected master monitors STRB-N and when
is referred to as PCDB-P when generated by
STRB-N is removed, the address, control,
or exiting from a function and PCDA-P when
and data (if a write operation) is placed on
entering a function. Assume that two func-
the INFIBUS. The selected master places
tions, the Parallel I/O and TTY Controller,
the address on the INFIBUS address lines,
are requesting INFIBUS access.  SRL1-N is
AB00-N through AB15-N (waveform E, figure
generated by both functions and is detected
3 ) . If the master is to write data into the
by the Bus Controller. The Bus Controller
function being slaved (addressed), it gen-
generates the select line, SEL1-N, and
erates RITE-N (waveform F, figure 3). If it
PCDB-P.  PCDA-P is coupled through and
is to read data from the function being slaved,
delayed by the CPU and Autoload functions
it holds the RITE-N line high. If the data
and trapped by the Parallel I/O. Trapping
being transferred is a 16-bit word, the
the precedence pulse enables the Parallel
master holds BYTE-N high and data lines,
I/O to gain INFIBUS access first. When the
DB00-N through DB15-N (waveform G, fig-
Parallel I/O completes its transfer, the Bus
ure 3), are used. If the transfer is to be an
Controller generates PCDB-P again (SRL1 -N
8-bit byte, the master generates BYTE-N
still being generated by TTY Controller)
and only 8 data lines, DB00-N through
which is trapped by the TTY Controller.
DB07-N, are used. The selected master
The precedence pulse serves to grant
now generates STRB-N which allows the
INFIBUS access to the function nearest the
requested data transfer to occur (service
Bus Controller first when two or more func-
cycle) and removes SACK-N which allows
tions are requesting INFIBUS access on the
the Bus Controller to select the next master
same priority level.
if it is requesting INFIBTUS access.
5 - 3 3 . When one or more masters are re-
5 - 3 5 .  If a second master is requesting
questing a DDT, the master or masters
INFIBUS access, the Bus Controller selects
generate SRLD-N (waveform A, figure 3).
this function in the same manner it selected
The Bus Controller senses SRLD-N and
the first master. While the second master
selects SRLD-N over other requests. The
function is being selected, the slave (ad-
Bus Controller then generates the select
dressed) function of the first master func-
signal, SELD-N (waveform B, figure 3),
tion recognizes its address on the INFIBUS
and the precedence pulse, PCDA-P (wave-
and the data is written into or the data
form C, figure 3). SRLD-N is received by
(waveform I, figure 3) is read out of the
all of the masters requesting INFIBUS access
s l a v e .  When the data transfer is complete,
but PCDA-P reaches the master nearest the
the slave generates DONE-N (waveform J,
Bus Controller first. This master prevents
figure 3) which causes the first master to
the precedence pulse from being coupled to
remove the address, control, and data (if a
the other masters. The master requesting
write operation) from the INFIBUS. Receiving
the INFIBUS access now generates SACK-N
DONE-N also causes the master to remove
(waveform D, figure 3) which notifies the
STRB-N from the INFIBUS. The second se-
BUS Controller of a successful selection and
lected master function senses the removal
prevents other functions from requesting
INFIBUS access during the time it is glen--
of STRB-N and places address, control and
era ted.  If SACK-N is not sensed by the Bus
data (if a write operation) signals on the
INFIBUS and a data transfer occurs as ex-
Controller within 2 microseconds after
plained for the first master. Upon comple-
SELD-N and PCDA-P are generated, the Bus
5-5

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