BUS CONTROLLER

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

Processor function service cycle begins.

dress in the range of FOOO 16 through FFFF 16

is assigned to each Processor function with

During the service cycle the Processor func-

the exception of the Bus Controller. Each

tion transfers the information to the INFIBUS.

These request and service cycles can over-

Processor slave is capable of recognizing

lap in time. While one function is perform-

its assigned address when it is on the

INFIBUS. Each slave is also capable of

ing a service cycle another function may be

placing its address on the INFIBUS data

performing a request cycle and when the first

lines when it is requesting INFIBUS access.

function completes its service cycle the

second function then performs its service

cycle.

5-25. Each Processor function has three

basic registers; the data register, control

5-28. Requests for INFIBUS access are

received by the Bus Controller on service

registers can be selected (addressed) by a

request lines which are assigned priority

master. The register that is to be selected

levels according to their communication

is determined by the value of the 4 least

function. There are three types of com-

significant bits of the 16-bit address. The

munication priorities; module selection and

data register is usually comprised of two

service, interrupt selection and service, and

registers, one which provides data from the

CPU selection and service.

INFIBUS to the external function and one

which provides data from the external func-

5 - 2 9 . Module selection and service occurs

tion to the INFIBUS. The control register

when a Processor master requires the INFI-

stores command words issued by the stored

BUS to perform a data transfer directly

software program which'start and stop

to or from the Core Memory or other

function operations. The status register

Processor functions. These data transfers

indicates to the CPU that the Processor

function and external device are ready and

are referred to as direct data transfers (DDT)

indicates any errors detected in the opera-

and are not under control of the CPU and

tion of the external device. Also, writing

stored software program. DDT transfers

into the status register causes that function

are the highest priority level transfers and

to be cleared.

take precedence over all other requests for

INFIBUS access. The SRLD-N request line

is activated when a DDT is requested.

5-26. BUS CONTROLLER. All communica-

tions between Processor functions are via

5-30. Interrupt selection and service occurs

the INFIBUS which is controlled by the Bus

on one of four assigned priority levels when

Controller. Communications on the INFIBUS

a Processor function requires the INFIBUS

are asynchronous `and bidirectional- (one

to perform a data transfer under control of

direction at a time). All communications

the CPU and stored software program. The

between Processor functions consist of two

four interrupt request lines, SRL4-N through

cycles, first the select cycle then the ser-

SRLl-N (level 4 through level 1 interrupts),

v i c e cycle. The primary purpose of the Bus

determine the priority of the interrupt re-

Controller is to allocate INFIBUS time to

q u e s t s . SRL4-N is the highest level priority

Processor functions on a priority basis.

interrupt request and SRL1-N is the lowest

The secondary function of the Bus Controller

level priority Interrupt request. All DDT

i s t o generate CFU internal interrupts

requests must be serviced before interrupt

for power fail, power restart, calendar

requests may be serviced in their order of

a n d clock stored software program up-

priority.

date, and operator attention.

5 - 3 1 . CPU selection and service occurs

5 - 2 7 . During the select cycle, a Processor

when the CPU requires the INFIBUS to ex-

function requests INFIBUS access and then

ecute the stored software program. CPU

the Bus Controller, depending on the priority

selection and service is also a DDT request.

of the request, grants INFIBUS access to the

However, these transfers on the INFIBUS

Processor function. When the Processor

have the lowest priority and the SRLC-N

function gains access to the INFIBUS, the

5-4