Decoder Section, Basic Logic Analysis

TM 11-6695-667-45/NAVSHIPS 0969-249-8010/NAVAIR 16-30APM123-2/TO 33A1-367-22

ampifier Q3 is controlled by receiver sensitivity

depends on the type of test in progress. After video

control A8R5. Adjustments are made with the

gate 2 is enabled, the reply video processed by the

equivalent minimum transponder set RF level (0

video amplifier is gated to video shaper DSS1.

Each video pulse triggers video shaper DSS1,

to 15 dbm) present at PROBE jack A15J24.

which produces 0.7-microsecond pulses. The video

Sensitivity control A8R5 is then adjusted until

shaper is a one-shot multivibrator containing

video amplifier Q3 output is sufficient is just drive

transistors A11Q1 and A11Q2 and provides 0 and

video shaper DSS1 through video gate 2 (c

1 outputs. Transistor A11Q2 produces the postive-

below). This action results in a just-accept con-

going 1 output, while A11Q2 simultaneously

dition. A voltage divider consisting of resistors

produces the negative-going 0 output. Both groups

A8R6, A8R7, and A8R8 connects the emitter of

of pulses are fed to the error detector (para 2-

A8Q2 to the base of A8Q1 to provide current feed-

14d). The positive pulses are also fed to line-drive

back for temperature compensation. Capacitor

gate 1 in the decoder section, where only the F1

A8C6, connected across A8R8, provides high fre-

or I/P pulses of a pulse train are gated (para

quency compensat ion. When A8Q1 conducts, the

2-14C(3)).

resultant negative-going signal at the emitter of

A8Q2 is coupled through capacitor A8C5 and re-

2-14. Decoder Section, Basic Logic Analysis

sistor A8R9 to video amplifier A8Q3. Video

a. Video-Enabling Functioning. Video-enable

amplifier A8Q3 and emitter follower A8Q4 are

DFF6 (fig. 8-3) provides the video-enabling volt-

temperature compensated by a voltage divider

age to video gate 2 (para 2-13c). This flip-flop

network similar to the one in video amplifier Q1.

multivibrator is initially reset by a decode-enable

Video amplifier A8Q3 is normally conducting and

pulse produced by the last (P3) interrogation

the negative input video pulse at its base decreases

pulse. The decode-enable pulse also triggers video-

this conduction. The increasing collector voltage of

enable delay DSS4, which generates a video-delay

A8Q3, in turn, increases the emitter voltage of

pulse. Video-enable delay DSS4 is a one-shot

A8Q4. To obtain a fast pulse risetime, capacitor

multivibrator containing transistors A10Q1 and

A8C8 is forced to discharge through resistor

A10Q2, and produces a 1.8-microsecond positive

A8R11 by the emitter action of A8Q4. This ef-

pulse (fig. 8-13). The output is taken from the col-

fective feedback to the base of A8Q4 forces it to

lector of transistor A10Q2, normally

conduct-

conduct at a faster rate. In discharging, capacitor

ing. When DSS4 is triggered, A10Q2 ceases

A8C8 blocks conduction through diode A8CR3

conduction for 1.8 microsecond. The trailing edge

until its charge potential approaches +12 volts.

of the resultant 1.8-microsecond positive pulse sets

This condition isolates the capacitor surge from

video-enable DFF6 and also triggers read delay

the + 12-volt source. The resultant video at the

DSS5 (e below ). Video-enable DFF6 is a flip-flop

emitter of A8Q4 is coupled by capacitor A8C16 to

multivibrator containing transistors A9Q1 and

either video gate 1 or video gate 2 (c below).

A9Q2 (fig. 8-12). In a set state, the 1 output of

c. Receiver Gating. Video gate 2 (fig. 8-3) per-

A9Q2 is high and enables video gate 2 (fig. 8-3).

forms as the receiver gate during all test set oper-

Thus, the receiver gate is enabled 1.8-microsecond

ations, except mode 4 tests. Mode 4 video is con-

after the trailing edge of the P3 interrogation

trolled by video gate 1 and gates this video signal

pulse.

to external equipment. Video gate 2 is enabled dur-

b. Receiver Gate Period and Video-Enabe Re-

ing self -test. operation by encode enable IFF1

set Functining. Line-drive enable DFF1, counter

(para 2-11) when FUNCTION switch A15S6 is

DFF3/DFF4, or the M1/M3 timing pulses ( (1)

at SELF TEST. During all other functions,

below ) conclude the receiver gate period by reset-

switch A15S66 connects gate diode A8CR11 to video

ting video-enable DFF6 (fig. 8-3). This action

enable DFF6 (para 2-14a). Video enable DFF6

removes the enabling voltage from video gate 2

provides an enabling voltage to video gate 2, 1.8

in the receiver section. A delayed 22-microsecond

microseconds after transmission of the last interro-

gation (P3) pulse. Duration of the gate period

M1 pulse controls the operation of DFF1 and

Change 4

2-19