RC Bus Status Interface CCA (A6)

TM 32-5865-069-24&P

3-3.11 RC Bus Status Interface CCA (A6). Refer to FO-4 a functional block

diagram of A6. A6 provides a control interface with RC Bus A. This allows the

AN/MLQ-34 computer to control the operation of the four CPD. In addition, A6 is

used to provide the computer with status data. A6 also buffers and repeats RC

Bus A. This allows the bus to be used to tune and control four receivers.

3-3.11.1 RC Bus Buffer. RC Bus A signals data, clock, and strobe are fed to

line-receivers U33A, U43A, and U43B respectively. The line-receivers are enabled

by POR* from the power-on-reset logic circuit (U26B, U26C). The CLOCK signal is

inverted by U4E to provide a CLOCK* signal. CLOCK* is buffered and inverted by

U27B and fed to the front panel of the RSPU as RC BUS A CLK MON. A line-driver

(P/O U32) drives the CLOCK OUT. Inverters U26A and U26F invert STROBE to provide

two signals STROBE* (1) and STROBE* (2). These signals are used to synchronize

the logic circuits on A6 with the RC Bus. STROBE* (1) is buffered and inverted by

U27A to provide RC BUS A STROBE MON at the front panel of the RSPU. STROBE is

driven out by the line-driver (P/O U32) as the STROBE OUT. DATA is buffered and

inverted by U23E and U27C to provide RC BUS A DATA MON at the RSPU front panel. A

line-driver (P/O U44) drives DATA out as RC BUS OUT. The 5 MHz reference is fed

to line-receiver U33B. This signal is buffered for use on A6 and also driven out

by the line-driver (P/O U52) as 5 MHz OUT. The logic circuits on A6 examine the

address-bits (bit O-5) in each data word. The logic of the address bits deter-

mines the mode of operation. When data-bits 3, 4, and 5 are all high (logic `1'),

A6 transmits STATUS DATA onto the bus. When data-bit 5 is low (logic `O'), A6

listens to the bus. In the listen mode, data-bits 6, 7, 8, and 55 are latched

from the bus. These data-bits are used to provide control signals for the CPD.

3-3.11.2 Address Storage. DATA from U33A is applied to the data/clock gate

circuit (U22C, U23A, U23B, U23D, U25). This circuit is enabled when the status

flip-flop (U1B) is reset by STROBE* (1) forcing STATUS* high. SERIAL DATA, from

the data gate circuit, is shifted into the data shift register (U11, U21, U41) by

XMT CLK. XMT CLK is the CLOCK* signal gated out by STATUS*. The address frame

shift-register (U34) counts the CLOCK* signals. After six CLOCK* periods the

event flip-flop (U15A) is set enabling event shift-register (U24). U24 shifts the

5 MHz (CLK) signal from line receiver (U33B). Four sequential control signals are

enerated by U24. The first is STORE ADDR. This signal is fed to address store

U31 . U31 latches the first six bits (address) in the data word held as parallel

data in the data shift register. The address-bits from the data word are fed to

status decoder, address comparator, and CPD address decoder circuits.

3-3.11.3 Status Decoding. The second control signal provided by U24 is STATUS

DECODE. This signal enables status decoder U13B. U13B examines address bits 3,

4, and 5. When all the bits are high, U13B sets U1B. STATUS* disables the data

gate circuit. The SERIAL DATA input to the data shift-register is inhibited. The

data shift register is reset preparing the circuit to transfer data out. If the

address bits are not all high, U1B remains in the reset condition (STATUS* high,

STATUS low).

3-3.11.4 Status Transmission. LOAD STATUS, the third control signal from U24 is

applied to the data shift register. CPD LOCAL 1-4, 150 Hz TONE RCVR 1-4, RS

POWER, RS TEMP, RSPU POWER (inverted by U53B), and RSPU TEMP (inverted by U53A)

are loaded into the shift register. These signals are shifted out as serial

STATUS DATA by RCV CLK. RCV CLK is the CLOCK signal gated in the data/clock gate

3-23