CPD Control

TM 32-5865-069-24&P

circuit by STATUS from U1B. STATUS DATA is fed to the line driver, P/O U44. The

line driver is gated by the output of the XMT flip-flop U2A. U2A provides the

XMT* signal. When XMT* is low, the line driver is enabled and drives STATUS DATA

onto RC Bus A.

3-3.11.5 Address Comparator. ADDR SEL 23-25 (BIT 0-2) are hardwired to provide

the unit address. These signals are fed to the (A) input of address comparator

(U42) with STATUS from U1B (BIT 5). BIT O, 1, 2, and 5 latched by U31 from the

data word provide the (B) input to U42. U42 is enabled by the fourth control sig-

nal from U24, ADDR COMPARE. When the two inputs to U42 are the same, the signal

(A) = (B) goes high. This signal is used to clock XMT and CPD address detector

flip-flops (U2A, U1A). UIA and U2A outputs are determined by the logic of U1B.

When U1B is set, U2A output XMT* enables STATUS DATA to be driven onto RC BUS A

and UIA is held reset by the STATUS* input to the CPD logic circuit. When U1B is

reset, XMT* is high preventing data from being driven onto RC Bus A. U1B provides

ENABLE CPD and enables the CPD address decoder U12.

3-3.11.6 CPD Control. ENABLE CPDfrom U1A sets the data 6-8 enable flip-flop.

(U3A, U22A, U26E) . The flip-flop provides the signal ENABLE CPD OATA 6-8 fed to

the CPD shift register circuit (U4D, U7, U22B, U22D). This signal allows bits 6-8

of the data word to be clocked into the CPD shift register. ENABLE CPD is also

used to enable a counter circuit (U4A, U5, U14A, U14B, U14C, U16). This circuit

counts CLOCK signals. When the count reaches three, the circuit provides the DIS

CPD DATA 6-8* signal. This signal resets the data 6-8 enable flip-flop and

inhibits data input to the shift register. When the counter circuit reaches a

count of 50, the CPD event pulse flip-flop (U4B, U14C, U14D, U15B) is clocked and

the CPD event shift register (U4C, U6, U23F) is reset. The output from the CPD

event pulse flip-flop is fed to the CPD event shift register. The 5 MHz (CLK) is

applied to the register which provides three sequential control signals. The

first signal is ENABLE CPD DATA 55. This allows the CPD shift register to store

data-bit 55. The second signal is STORE CPD DATA. This is decoded with the two

CPD address-bits in CPD address decoder U12. U12 output enables one of the four

CPD address lines CPDADDR (O, 2, 4, 6). Each address line controls one of the

four CPD control registers (U35-U38) and one of the four CPD reset generators

(U18, U28) . Data from the CPD shift register is loaded into the addressed CPD

control register. Decoders U45-U48, one dedicated to each CPD control register,

decode the latched data (BIT 6-8). The decoder provides the appropriate bandwidth

information for the addressed CPD, as CPD 1 BW SEL - CPD 4 BW SEL. Latched data-

bit 55 provides the sensitivity control information for the addressed CPD, SENS

CONT 1-4. The appropriate CPD reset generator provides a reset signal. This

signal CPD RESET 1-4 is used to dump the integrator charge in the selected CPD.

The third control signal DISABLE CPD*, resets the counter and CPD address detector

circuits.

3-3.11.7 Indicator Lamps. The outputs from the four CPD, CPD 1 LOCAL * thru CPD

4 LOCAL* are used to drive front panel lamps. Each signal is fed to a pulse

stretcher circuit (U9, U19). The outputs of the pulse stretcher are fed to AND/OR

INVERT gates (U29, U39). The input signal is also fed via an inverter (U53C,

U53D, U53E, U53F) into the gate. The gate output is the longer of the two input

signals. This arrangement allows the lamps to be lit for transient as well as

continuous activity in the CPD. The operation of the lamp circuit for the 150 Hz

detectors is similar. A LAMP TEST* input to the lamp drivers causes all lamps to

light.

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