PAN Processor

TM 32-5865-069-24&P

received from the bus. The data is decoded to control: attenuation with a 60 dB

range, bandwidth in eight steps and the video/WBIF selection used to determine

which input signal is processed. RC Bus timing is described in figure 3-1. Data

format for RC Bus B is shown in figure 3-4 and figure 3-5.

3-2.4 PAN Processor. The PAN processor is comprised of: an analog front end

(A14 and A20), a microprogram sequencer (A9) with microprogram memory (A8), a high

speed data memory (All) and an address generator (A1O). A12 provides the proc-

essor interface functions and a high speed A/D converter which allows continuous

sampling of the signal input. These items form a digital data processor which

converts the received signal, WBIF or video as required, into a digital represent-

ation of its frequency spectrum using a Fast Fourier Transform (FFT) algorithm.

The following paragraphs briefly describe the operation of the processor.

3-2.4.1 Analog Front End. Received signal selection, display bandwidth, and

attenuation are controlled by the operator at the RCDU. Data, transmitted from

the RCDU to the RSPU on RC Bus B, is collected and formatted by RC Bus Interface/

8085 CPU, A7. A7 transfers PAN processor control data to 1/0 Register, A12, using

the DATA BUS. A12 decodes the data received from A7 to provide control signals

for down converters A14 and A20. IF SEL RCVR 1-4 are used to select from one of

the four WBIF signals applied to A20 (RCVR 1 WBIF thru RCVR 4 WBIF). VIDEO CONT

RCVR 1-4 select from one of the four video inputs applied to A14 from A5. The

signals 10 DB, and 20 DB1 thru 20 DB3 control attenuation of the selected signal

in A14 and A20. The selected WBIF signal input is down converted in A20 and

appears at the output as the SELECTED IF signal. SELECTED IF has a center fre-

quency of 2 MHz and is processed in A14 to provide two versions of the IF signal

(one wideband signal with center frequency 2 MHz and one narrowband signal with

center frequency 200 kHz). These two signals are fed to a selector circuit

together with the selected video signal. The output signal from A14, ANALOG IN,

is selected from the three signals by control inputs NBIF*, WBIF*, and VIDEO*.

ANALOG IN is fed to A12 for conversion into digital data.

3-2.4.2 Signal Data Processing. Analog-to-digital conversion of the ANALOG IN

signal is performed on A12. Conversion is controlled by the clock signal PICCLK

from Control Sequencer, A9. When the ANALOG IN signal is either too small or too

large to provide valid data for processing A12 outputs the signal PDSIV to A7.

This signal is transferred to the RCDU where it is used to warn the operator that

the displayed data may be invalid. Control signals are derived from data fed to

A12 from A7 on the DATA BUS. These signals, which determine FFT size and sampling

rate, are held in storage registers to await transfer to A9 on the C-Data bus

(CDAT) . The transfer of CDAT to A9 followed by the `valid data' flag CIVLD, start

the data processing cycle. Seven BUS CONTROL signals organize the transfer of

data between the processor circuit cards. The A-data bus (ADAT), and the B-data

bus (BDAT) are used for the transfer of signal data. The Immediate-data bus

(IDDAT) is used to transfer general housekeeping data. Control signals

(SEQUENCER CONTROL) instruct A9 to ensure the proper address word is provided for

conditional branches in the program. Status flag signals are provided from A12

and address generator A1O. A1O is used to perform the processing operations on

the signal data and to organize data in 4K RAM (All). Address bus MADDR is used

for this task. The signal MWRCYC* controls the data memory. All data processor

clocks are provided by A9. Four signals, RCVR 1 DELAY GATE thru RCVR 4 DELAY

GATE, are fed into A12. The leading edge of the gate signal is coincident with

the presence of valid data in the receiver output signals (WBIF/VIDEO). The

appropriate gate signal, selected from the four inputs, is stretched in A12 and

3-5