Communication Processor Transceiver I/O Module Test.

TM 32-5811-024-14&P

(b) The parallel-to-serial converter. (serially shifts its 16-bit word to the HID (high indicator data) lines

via line driver U20A.)

(7) Time state T4. The output of the 16-clock pulse counter goes low when the 16th clock pulse is counted

and the 16th HID bit has been transferred to the control-indicator. This low clears the output clock latch to terminate the

clock and generates an HILP (high indicator load pulse) pulse. This pulse is applied to the control-indicator CCA A1 via

line driver U19B. HILP loads the transferred HID word into lamp drivers to light the status lamp.

5-15. Communication Processor Transceiver I/O Module Test.

a. General. (See figure FO-16) Transceiver test CCA A10 generates the test signals required to check the

communication processor transceiver I/O (ECA) A30. The major components are a PR code generator and a 10-Hz

b. PR Code Generator. The PR code generator (see figure 5-9) provides a pseudorandom code that repeats every

63 bits. The generator consists of three shift registers, a bipolar-to-TTL converter, 63-bit feedback (exclusive OR) gate

U13, output circuits, a PR zero preset circuit, and a PR code test circuit.

XMIT CLK is a bipolar clock derived from the communication processor transceiver I/O ECA under test. This clock is

converted to TTL level by U3 and U16. The resulting TTL clock at J5 drives the shift registers and PR zero preset circuit

latch U7B. The clock input to the three 4-bit shift registers (shift register 1, U10; shift register 2, U5; and shift register 3,

U1) circulates the data from their input to output port Ul-13. The resulting PR code output is applied to the

communication processor transceiver I/O ECA in bipolar form via the output circuits. Feedback gate U13 responds to the

2A and 2B outputs of shift register 2 by modifying the shifted bits to provide pseudorandom encoding. This feedback

arrangement provides a PR code that repeats every 63 clock cycles.

If abnormal operating conditions occur, such as digital processor test set power loss and recovery, all PR code bits

become 0 and the PR code generation capability of CCA A10 is lost. As a result of this condition, only 0 bits may be

generated. The PR 0 code preset circuits respond to this condition by ORing all shift register 0 bit outputs to provide a

low D input to latch U7B. The next TTL clock resets the latch. The low Q output of the reset latch loads all ls into the PR

code shift registers to restore the PR code generation capability.

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