Detailed Description

TM 32-5811-024-14&P

driver U28A. The leading edge of this 10- (high output load pulse) loads switching data from the front panel into CCA

A2 of the control indicator.

(2) Time State T1. The positive-going transition of HOLP clocks sets input clock latch U30B. The resulting

high latch (Q) output enables clock gate U32B for an interval that begins with time T1 and ends during time T2.

(3) Time state T1+. Once enabled, the clock gate transfers a 50-kHz IHOC (indicator high output clock) clock

to three places:

(a) IHOC is transferred to the control-indicator CCA A2 to shift data from CCA A2 to the digital processor

test set CCA A9. This serially shifted control-indicator HOD (high output data) is transferred to the serial-to-parallel

converter via HOD line receiver U35B.

(b) IHOC is applied to the serial-to-parallel converter to load the input HOD serial data.

(4) Time state T2. When 32 clock pulses are counted, 32 HOD bits are loaded into the serial-to-parallel

converter. The 32nd clock pulse causes a 10-ps pulse to be generated at J7. The leading edge of this OUTPUT pulse

clears input clock latch U30B. The resulting low Q output inhibits the clock gate during T2, terminating the IHOC output.

The fully-loaded serial-to-parallel converter now provides a 32-bit parallel output to the test response matrix circuits

of CCA A9. These bits are predetermined, based on the switching selection on the communication processor control-

indicator. The BCD-coded platform designator 1,2,4 bits and relay platform designator 1,2,4 bits are decoded to provide

respective PLDZ 1 thru 5 and RLP 1 thru 5 bits. These inputs to the matrix result, in a parallel 16-bit output word that

lights a control-indicator status lamp. The negative transition of the OUTPUT (J7) pulse loads the matrix 16-bit output

word into the parallel-to-serial converter.

(5) Time state T3. The positive transition of the OUTPUT pulse at J7 clocks and sets output clock latch U30A

to output the 16-bit word to the control-indicator.

(6) Time state T3+. The high Q output of output clock latch U30A enables output clock gate U32A, providing

a 50-kHz IHIC clock at J3. This IHIC (indicator high input clock) clock drives the following:

(a) The 16-clock pulse counter.

5-24