Communication Processor Control-Indicator Interface Test Function.

TM 32-5811-024-14&P

(2) Time state T1. The communication processor CCA A20 responds to the low IHUD by generating a low

HOLP (high output load pulse) signal, which is synchronous with an internal clock. HOLP is inverted by line transceiver

U9A (and CCA A7) to provide a positive signal that clocks and (since its D input is high) sets CLR latch U2 during the

low-to-high transition and loads the parallel-to-serial converter (U3-U6).

The Q output of the CLR latch momentarily goes low to clear the XMIT and TEST latches. The resulting high Q

output of the XMIT and TEST latches drives NAND gate U8A low to immediately restore CLR latch U2B to the reset

condition.

(3) Time state T2-T3. Approximately one-half clock period after +HOLP is generated, the communication

processor generates HOC (high output clock) pulses. Thirty-two of the clocks are generated, in 16-pulse bursts, to

serially shift the contents of the 32-bit serial-to-parallel converter from CCA A7 to CCA A20 via line transceiver U7A and

the HOD (high output data) lines.

(4) Time state T4+. The communication processor responds to the test STATUS/CMD word by applying an

appropriate 16-bit response word to CCA A20 and initiating the next transfer sequence. CCA A20 generates a clock,

IHIC (indicator high input clock), to transfer the response word, HID (high indicator data), to the digital processor test set

CCA A8. The IHIC clock is applied to the serial-to-parallel converter via line receiver U1B to serially shift HID data into

the converter via line receiver U1A. Sixteen clock pulses completely load the 16-bit data and present this response word

to output latch U3 and U5 in a parallel format.

(5) Time state T5-T6. A positive 2-s HILP (high indicator load pulse) signal is activated, concurrent with the

16th or last IHIC pulse. This pulse is inverted by line receiver U2A to provide a negative version at J4. The low-to-high

transition of this pulse transfers the parallel 16-bit response word to the lamp drivers via output latch U3, U5. These

lamp drivers then light the digital processor test set COMMAND DISPLAY OCTAL DISPLAY according to the 16-bit

response word code.

The HRFI output of the communication processor CCA A20 is applied to the digital processor test set CCA A8

independently of the 16-bit word. HRFI (high radio frequency interference) is active when low and drives the DFD9

DPTS bit.

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