Communication Processor Control-Indicator Interface Test Function

TM 32-5811-024-14&P

(6) Time state T4. Enabled by the constantly high RDY-PROCEED output of the digital processor test set

serial interface test CCA A6, the unit-under-test serial interface responds to digital processor inputs by sending a high

IMR-MODE and PROCEED-RDY output. On serial interface test CCA A6, U2E and U12B of the I/O handshake logic

drive the MODE line high as a result of the high +IMR-MODE input. Gates U12A and U2D provide a high output in

response to the high PROCEED-RDY input. These two highs drive I/O gate U4A, U2C high, enabling CLK IN receiver

U6B.

(7) Time state T5. Responding to digital processor control, the unit-under-test serial interface CCA provides a

16-clock pulse and 16 serial data bits. These inputs are applied to receivers U6B and U6A/U2B, respectively. The data

constituting the test response word of the unit under test are loaded into the serial-to-parallel converter of the serial

interface CCA by the INPUT CLK (J7).

(8) Time state T6. The 16th INPUT CLK pulse loads the test response word into the serial-to-parallel

converter. The output of this converter feeds the octal COMMAND DISPLAY OCTAL DISPLAY indicators on CCA A12

for visual verification of the correct response code and proper functioning of the unit under test serial interface CCA.

NOTE

The front-panel CP STATUS/SER INT switch (S7) must be in the SER INT position to enable the

serial-to-parallel converter on CCA A6. In this position, S7 provides a false (low) SIT (serial

interface test) DISABLE, which allows the serial-to-parallel converter output to drive the

COMMAND OCTAL DISPLAY on CCA A2.

b. Self-Test. The serial interface test CCA can be operated in the self-test mode by connecting W239P1 to J10 of

the digital processor test set. This forces +IMR high,, shorts the constant high +RDYPROCEED output to the

+PROCEED-RDY input, and provides a low COFORCE line. This arrangement permits the output test word to be loaded

back into the serial interface test CCA.

The high +IMR MODE signal, in conjunction with the high +PROCEED-RDY input derived from the shorted +RDY-

PROCEED output, drives the I/O gate high. This high enables the feedback +(NFC) CLK IN input. The low COFORCE

line enables output transmitter U15B via U5B and forces exclusive NOR U1B to invert the outgoing clock (CLK OUT) to

provide the appropriate phasing of the feedback clock (CLK IN).

5-12. Communication Processor Control-Indicator Interface Test Function.

a. General. (see figure FO-13). Logic control CCA A7 in conjunction with lamp driver CCA A8 simulates a control-

indicator to test the ability of the communication processor to receive, assimilate, and respond to control-indicator

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