RF Processor Simulation Function.

TM 32-5811-024-14&P

Table 5-3. Typical Digital Processor Control Sequence - Continued

Switch

Circuit Activity

NORM ROM/DPTS ROM (continued)

The digital processor test set diagnostic program

responds to the address by generating a 24-bit

instruction word, which is applied to the digital processor

instruction bus via diagnostic buffer CCA A4, the cabling

RIN0 thru RIN23 lines, and the enabled ROM extender

CCA of the unit-under-test digital processor.

BREAKPOINT switch (S6) (pressed)

A high BRKPT signal is applied to the unit-undertest

processor timing CCA.

This input activates the

breakpoint logic circuits only when the digital processor

is in the HALT condition. Once activated, this logic will

cause the digital processor to HALT when the

ADDRESS set on the CPU CONTROL panel is reached.

Once this breakpoint address is set, the operator may

restart the digital processor by setting the DPTS RUN

switch (S2).

RUN (S2) (pressed)

A RUN signal goes high and a RUN signal goes low to

defeat the processor timing HALT logic, allowing the

digital processor to execute the diagnostic ROM

instructions. When the breakpoint address set on the

CPU CONTROL panel ADDRESS switch is reached, the

digital processor again halts, if the breakpoint logic has

been previously activated by the BREAKPOINT switch.

SINGLE STEP (S4) switch (pressed) Circuit Activity

S4 sends a low (ground) SGLST signal and a high

SGLST signal to the halted unit-under-test processor

timing CCA logic. The logic responds by momentarily

defeating the HALT condition, allowing the digital

processor to execute one instruction cycle. ,The digital

processor then halts at the end of this cycle.

5-10. RF Processor Simulation Function.

a. General. (see figure FO-11) RF processor simulator CCA A5 is used in place of an RF processor to test the

digital servo group circuits of a df control (see figure 5-2). Basically, this CCA performs a closed servo loop test, which

exercises the overall servo nulling capability of a df control.

5-10