Analog Frequency Output

TM 11-6625-922-15

i. Analog Frequency Output A3 (fig. 9-20). This

by the DELAY ZERO ADJ front panel control.

circuit provides an analog delay output which is a dc

g. Input Amplifier and Demodulator A6 (fig. 9-16).

level that varies directly with the delay reading in the

The input to this circuit is a modulated sine wave. The

instrument. When an external marker input is applied, a

output is a full-wave rectified sine wave with the

series of pips is superimposed on this dc level whenever

envelope of the peaks following the low-frequency

the frequency input approaches and passes the

modulating sine wave. Amplifiers A1 and A2 are

frequency of the external marker input. The frequency

integrated circuit dc amplifiers. Resistor R1 is the input

input is a square wave, and the analog frequency output

resistor, and resistor R3 is the feedback resistor for Al.

is a dc level proportional to the logarithm of the input

The stage has an overall gain of 31.6 (R3/R1). Most of

frequency. Both outputs become more positive as the

the other passive components connected to the

analogous parameter increases. Transistors Q1 and Q3

integrated circuit are used for frequency compensation.

are a Darlington amplifier, the output of which feeds

Amplifier A2 has resistor R7 and variable resistor R9 in

push-pull switch Q4, Q5 to produce a square wave at

the feedback loop. Transistor Q2 is a current source for

TP1. The external marker input applied through emitter-

the differential amplifier, full-wave demodulator Q1 and

follower Q6 is used as the supply voltage in mixer Q7,

Q3. The output signal from A2 is applied to bridge

Q8. These two transistors are operated in the inverted

diode CR2 through CR5 to start turning Q1 on during the

mode, and alternately switched on and off by the input

positive half cycle and to start turning Q3 off during the

signal. The mixed signal appears at TP2, and is then

negative half cycle, causing the full-wave demodulation.

sent through emitter-follower Q12 to a two-section, low-

Transistor Q4 is an emitter follower. Transistor Q5 is an

pass filter, R38, C16 and R39, C18. This ac signal is

emitter follower for the complete signal from the output

added to the filtered delay pulse input signal (filtered by

of A2 before being applied to the meter circuitry.

R45 and C20) at the input of emitter-follower Q15. The

h. Output Amplifier and Meter Amplifier A12 (fig.

frequency input is also applied to emitter-follower Q2,

9-18). This module contains a 30-db amplifier, a 7.8-db

and then to the diode-capacitor-resistor network. The

amplifier, and a meter driving amplifier. It also provides

capacitor values differ by factors of 10, to stagger the

a dc analog output proportional to the meter indication.

log characteristics of the diodes and to produce a four

The input modulated signal is applied to emitter-follower

decade dynamic frequency range. The log voltage thus

Q1, then routed through a variable resistor (front panel

generated is fed to feedback amplifier Q9 through Q13.

TRANSMIT LEVEL DBM control) for attenuation. The

j. Delay Output A8 (fig. 9-22). This circuit drives

signal is sent to the integrated circuit amplifier A1, which

the DELAY meter, which gives a direct indication of the

with output driver stage Q4, Q5, feedback resistors R26

phase difference (or difference in time) between a

and R9, and input resistor R6, gives an overall gain of

reference timing signal and the demodulated input

approximately 32. Stages Q6 through Q12 represent an

signal. Four precise timing signals (pulse 1, pulse 2,

amplifier which, with its input resistor R33 and feedback

pulse 3, and strobe) are combined in AND gate Q4 to

resistors R36 and R37, give an overall gain of 2.4 (7.8

produce a negative pulse at TP1 whenever all four

db). There are two differential stages Q6, Q8 and Q9,

inputs are at logical ONE (positive voltage). The output

Q10. Stage Q11, Q12 is a push-pull emitter-follower

of integrated circuit flip-flop M1 (TP2) goes positive

output stage. A signal level input at pin K or a

when the pin 10 input goes negative (ground). Test

percentage modulation input at pin L is selected by the

point TP2 goes to ground when the pin 2 input, which

% MOD - RECEIVE LEVEL-TRANSMIT LEVEL switch.

corresponds to the demodulated input signal, makes a

Integrated circuit amplifier A2 drives diode-capacitor

negative-going transition. The output of the flip-flop,

network CR6, CR7, and C12, C13 in a feedback

therefore, remains positive only during the time between

configuration. A dc voltage proportional to the input is

the occurrence of a reference timing pulse and the

developed across C12 and C13 for driving the meter.

leading edge of the modulation input signal. The two

Network R31, R32, and C16 provide dc feedback for

signals are at the same frequency; therefore, the flip-

bias stability, but little ac feedback so that the ac signal

flop output gives a direct indication of the relative timing

can be amplified. The signal applied to emitter-follower

or phase difference by its duty cycle. Transistors Q5,

Q3 is rectified and filtered by CR1 and C3, then fed to

Q7, and Q8 are used as a switch to generate the two

emitter-follower Q2 to provide the analog meter dc

levels of ground and +12 volts at TP3.

voltage.

5-13