Integrated Circuits

TM 11-6625-922-15

these signals by enabling one AND gate and inhibiting

No.

Types

Model No.

the other two AND gates (M1/A10). The signal goes

Dual 4-input gate

MC830P

through an OR gate (M7A/A10), and is used to reset the

Power gate

MC844P

gate signal. Two flip flops are tied together to operate

Quad 2-input gate

MC846P

as an ac set-reset flip-flop; that is, the flip-flop responds

Clocked flip-flop

MC845P

only to logic level transitions, not dc levels. The gate

Dual flip-flop

SN7473N

signal is taken from such an ac flip-flop (M14/A10,

Decade counter

SN7490N

M15/A10), being set by the 100-Hz signal, which is

Decoder/driver

SN7441N

synchronous with the other timing signals. When the

gate signal is reset, the display control flip-flop

b. Logic Circuits. The first types listed in a above

(M16/A10, M17/A10) is set, thereby holding the lighted

are logic circuits, and the following positive logic

numbers in the readout display. The display control flip-

definitions apply:

flop is reset by 1 Hz, giving a display time of 1 second

Logical 1 = high voltage (+2.4v to +5.0v)

(or 0.9 second in the .1 SEC position of the COUNTING

Logical 0 = low voltage (0.0v to 0.5v)

TIME switch). The reset control is activated for 1 period

Note. Any unused input is equivalent to a logical 1.

of the 100-Hz signal (10 milliseconds (ms)).

c. Gates (A, fig. 5-6 and A, fig. 5-7) The gates

(2) The input sine-wave signal is squared by

(first three types listed in a above) are all NAND gates

the input circuit (Schmitt trigger ST1/A1), and then sent

and operate as follows:

to the input of an AND gate (M11A/A1). A gate signal

Inputs

Output

on the other input of the AND gate (M1A/A1) allows

Any input = 0

input pulses to pass for a time, as selected by the

All inputs = 1

COUNTING TIME switch. The signal then goes through

d. Flip-Flops. The two outputs of the flip-flops

five decade registers (M2, 3, 4, 5, 6/A1). Each decade

(types 4 through 6) should usually be opposite logically

counter then drives a decoder/driver (M7, 8, 9, 10,

(one output should be a logical 1 and the other should

11/A1), which drives a lighted numerical indicator (DS1,

be a logical 0). For the TS-2669/GCM, the flip-flops are

2, 3, 4, 5/A1). At the end of the counting interval, the

used mostly as frequency dividers. The timing for the

number is displayed for about 1 second, the register is

divide-by-2 mode is shown in B, figure 5-7. Note that

reset, and the process repeated.

the flip-flop can change state on the 1 to 0 transition of

c. Synchronization Logic (fig.

5-4).

SYNC

the clock input. The flip-flops also have a dc input for

pushbutton S12 provides a means of zeroing the delay

resetting (or setting) that overrides the clock input.

reading for a reference carrier signal, when operating in

These inputs are used for establishing the desired initial

the end-to-end mode. When two oscillators are at

conditions.

exactly the same frequency, they can still have an

e. Clocked flip-flop (MC845P) (C, fig. 5-6). This

arbitrary phase relationship.

When the SYNC

flip-flop operates according to the following chart:

pushbutton is depressed, most of the flip-flops in the

n+1

timing logic are reset to zero by M20/A10 and M21/A10.

S1 (pin 2) S2 (pin 3) C1 (pin 9) C2 (pin 8) Q (pin 4)

While the pushbutton is still depressed, the next edge of

the incoming modulating signal allows the counting logic

to free run. In this way, the two oscillators can be

synchronized. The pushbutton logic is designed so that

as long as the pushbutton is not depressed, all counting

logic can run normally. The Strobe flip-flop (M1/A9) is

preset to a one, since the decoding logic lags the timing

logic by one-half a clock period to prevent false

triggering.

Presetting of the Strobe flip-flop

compensates for the half period offset.

Notes:

1. x-state of the input does not affect the state of the circuit.

5-6. Integrated Circuits

2. U-Indeterminate state.

a. General. Several types of integrated circuits are

3. A logical 0 applied to the CD input clears the flip-flop to 0.

used in the TS-2669/GSA1. This paragraph contains a

4. A Logical 0 applied to the SD input sets the flip-flop to 1.

brief description showing their general characteristics

and method of operation.

5-7