Direct rf connection test count.

TM 11-6625-667-45/NAVAIR 16-30APM123-2/TO 33A1-3-367-22

pose. The counters are enabled after the PUSH TO

ducting and its positive-going output causes the re-

TEST switch is activated, and a delay equivalent to

ply rate evaluator to provide an ACCEPT indica-

50 prf periods elapses. When the switch is activated

tion. If less than 56 time-decoded pulses are re-

the 28-volt supply charges capacitor A2C9 through

ceived, readout control A2FF7 remains in a reset

resistor A2R22 (fig. 8-41 (2)). After the effective 50

state. Inverter A2Q4 is, therefore, conducting for a

prf delay constant, the voltage level will be suffi-

full prf period and causes the reply rate evaluator to

cient to cause count delay amplifier A2M18C (fig.

produce a REJECT indication. In either case, the

8-38 (2)) to conduct. Regulator diode A2VR4 holds

count and test indication is held until the PUSH TO

the voltage at this level. The negative-going output

TEST switch is released. Additional counting, how-

o f the count delay amplifier inhibits gate

ever, is inhibited by a prf counter after 64 prf peri-

A2Q6/A2Q7, therefore, the reset level is removed

ods.

from both counters.

(2) Direct rf connection test count. This opera-

b. Time-Decoded Video Counting. Test indica-

tion requires 16 consecutive correct replies (within

tions are dependent on the number of time-decoded

64 prf periods) for an accept condition. In addition

video pulses received within 64 prf periods. Each

to the counter, a counter error reset circuit is en-

time-decoded video pulse from the mode 4 interro-

abled, When the RAD-DIR switch ,is set at DIR,

gation equipment is counted by the time-decoded

counter output gate A2M19B is inhibited, Gate

video counter. The operation is initially started

A2M19A and counter reset gates A2M15A and

with the triggering of time-decoded video delay

A2M15B are enabled through A2FF7. The latter

A2SS1 (fig. 8-38 (2)) by the output of enable gate

two gates are part of the counter error reset circuit.

A1M18A which produces a 267-microsecond pulse;

This circuit senses whether mode 4 decode video

its trailing edge triggers time-decoded video gate

was present and only a single reply was received

enable A2SS2. The time-decoded video pulse from

during a prf period. The counter trigger from enable

the mode 4 interrogation equipment can then be

gate A1M8A sets video sensor enable A2FF15 and

gated to the time decoded video counter. This pulse

its positive-going 1 output enables decoded, video

is in response to the decoded video from the test set

sensing gate A2M14A and counter reset gate

mode 4 decoder section; A counter output gate cir-

A2M15A. Decoded video, gated by gate A2M14A, is

cuit is controlled by the RAD-DIR switch, which se-

coupled by inverter A2M14B to reset A2FF15. If

lects a count of 16 or 56. The count of 56 is selected

the decoded reply is missing, the high 1 output of

when radiation tests are to be performed. A count

this flip-flop will be present when one-shot A2SS2

of 16 is selected for direct rf coupling tests.

is triggered by a subsequent counter trigger; there-

(1) Radiation test count. The RAD position of

fore, counter reset gate A2M15B is gated on and a

switch A15S9 inhibits gate A2M19A and enables

counter reset signal is applied to the counter

gate A2M19B. In this state, gate A2M19B is gated

through gates A2M18B and A2Q5. If two replies oc-

on at the count of 56 by the counter. The 1 outputs

cur during a prf period the -- of flipflop A2FF15

of A2FF4, A2FF5, and A2FF6 are high when at

goes high upon the arrival of the first decoded pulse

least 56 time-decoded video pulses are received. The

and enables counter reset gate A2M15A; therefore,

gating of A2M19B sets readot it control A2FF7 and

the second reply will

its 0 output goes low. Inverter A2Q4 then stops con-

Change 4

5.1-3