Mode 4 Reply Evaluation Section

TM 11-6625-667-45/NAVAlR 16-30APM123-2/TO 33A1-2-367-22

to amplifier A1Q6. This amplifier effectively con-

jack and causes the mode 4 interrogation equipment

trols receiver sensitivity for mode 4 operations. An

to respond, through MODE 4 jack after a delay of

168 sec, with mode 4 challenge video. These pulses

adjustment is performed after the initial test set re-

ceiver sensitivity is established while in an SIF

are coupled by inverter A5Q16 to M4 challenge

mode. Then, the test set is set for mode 4 operation

shaper A1SS6 which produces 0.5-microsecond

and control A1R43 is adjusted while the PUSH TO

(nominal) pulses at its 1 and 0 outputs. The duration

TEST switch is continually pressed and released

is adjusted by control A1R32, for 0.5-microsecond

with a pause between each action. Such action is

pulses at the transmitter output. Differences in du-

necessary since a mode 4 test indication is locked

ration are because of inherent pulse stretching at

until the PUSH TO TEST switch is released. The

the transmitter. The positive-going -- output is cou-

output of A1Q6 is gated by decode gates A1M1A

pled by inverter A1Q4 to drive the main modu-

and A1M5A to frost decode shaper A1SS3 and M4

lator driver in encoder module A4. The negative-go-

line drive shaper A1SS4, respectively. Each of the

ing 0 output is coupled by inverter A1M8D to ena-

three reply pulses trigger these one-shots. The 0.3-

ble gate A1M8A and ISLS line drive gate AlM8B.

microsecond pulse output of A1SS3 is applied to re-

The first pulse gated by A1M8A triggers video en-

ply coincidence gate A1M6B. The 0.7-microsecond

able delay A1SS5 and time-decoded video gate de

pulse output of AlSS4 is coupled by MODE switch

lay A2SS1, and sets video sensor enable A2FF15. A

A155-C to line drive gate 2 (module A10). Gated

gated pulse is also coupled by inverter A1M8D to re-

pulses are amplified by delay line driver A10Q7 and

set M4 decode enable A1FF2 and set M4 ISLS en-

applied to delay linee A6DL1. Pulses that appear at a

able A1FF3. This action disables enable gate

1.8microsecond tap are coupled by amplifier A1Q2

A1M8A and ISLS line drive gate A1M8B and en-

to decode gate A1M1B. Each gated puke triggers

ables ISLS trigger gate A1M9A. The single pulse

second decode shaper ASS2. Pulse that appear at a

output of line drive gate A1M8B is coupled by

3.6 microsecond tap are coupled by amplifier A1Q1

MODE switch A15S5-C to module A10. The pulse

to decode gate A1M1C. These gated pulses trigger

is gated by line drive gate 2 and coupled by delay

third decode shaper A1SS1. The outputs of A1SS2

line driver, A10Q7 to delay line A6DL1. These cir-

and A1SS3 are, therefore delayed, and then applied

cuits are time-shared with the SIF test functions.

to the reply coincidence gate. When the third pulse

The pulse is delayed for 8 microseconds and coupled

from oneshot A1SS3 is in coincidence with the sec-

by M4 amplifier A1Q3 to ISLS trigger gate A1M9A.

ond pulse from one-shot A1SS2 and the first pulse

The gated delayed pulse is coupled by MODE switch

from one-shot A1SS1, the reply coincidence gate is

A1SS5-E to trigger P2 shaper ISS2 (module A4),

gated on. If a reply pulse is miming or positioned in-

and by inverter A1M9B to reset M4 ISLS enable

correctly, one of the shaper outputs will not appear

A1FF3. The M4 ISLS pulse output of ISS2 is 0.5

in coincidence with the others; therefore, a coinci-

microsecond and is applied to P2 modulator driver

dence puke will not be gated by the reply coinci-

A 5 Q 1 7 / A 5 Q 1 8 on main modulator driver

dence gate and a video count is then inhibited. A

A4Q11/A4Q12 (modules A5 and A4, respectively).

gated coincidence pulse is coupled by inverter AlQ5

The resultant challenge video that appears at the

and video gate 1 (module A8) to trigger M4 shaper

transmitter will include the ISLS pulse spaced 8

A8DSS6. The 0.5-microsecond pulse output from

microseconds from the first mode 4 challenge video

A8DSS6 is coupled by amplifier A8Q7, through the

pulse.

MODE 4 jack, to the mode 4 interrogation equip-

b. Mode 4 Reply Decoding. Mode 4 video decode

ment. The pulse is also applied to the decoded video

enabling is performed by reply video enable A1FFL

sensing gate A2M14A. This equipment returns a

The first challenge video pulse, gated by enable gate

time-decoded video pulsee to the mode 4 reply

A1M8A triggers video enable delay AlSS5 to pro-

evaluation section.

duce a positive 150-microsecond pulse. The trailing

5.1-3. Mode 4 Reply Evaluation Section

edge of this puke sets reply video enable A1FF1,

and its positive going 1 output enables decode gates

a. General. This section determines whether a

sufficient number of correct replies within 64 prf

A1M1A, A1M1B, A1M1C, and A1M5A. Mode 4 re-

periods were processed. It contains two counters

plies are detected and processed by the receiver sec-

and time-decoded video enable circuits for this pur-

tion, and coupled from video amplifier module A8

5.1-2

Change 4