Error Detection Circuit.

TM 11-6625-667-45/NAVSHIPS 0969-249-8010/NAVAIR 16-30APM123-TO 33A1-3-367-22

the output goes low and resets video enable DFF6.

amplifier A10Q10 and Q11, then gated by the

In emergency operation the first two M1 pulses

delay-line output gate to comparison pulse shaper

have no effect on the emergency gate. When the

DSS2.

third M1 pulse triggers counter section DFF3, its

(2) Comparison pulse shaper DSS2. Com-

1 output again goes high. A positive-going volt-

parison pulse shaper DSS2 shapes the delay-line

age does not trigger counter section DFF4; there-

pulse output. Each delay-line pulse triggers DSS2,

which simultaneously produces both a positive-

fore, the 1 outputs of both sections are high and

and negative-going 0.5-microsecond pulse (fig.

gate on the emergency reset gate. A fourth M1

pulse again triggers the counter, causing both sec-

8-4). Comparison pulse shaper DSS2 is a one-shot

tions to go to a reset state. Thus, the gating volt-

multi vibrator containing transistors A11Q3 and

ages are removed from the emergency reset gate,

A11Q4, with A11Q3 the normally conducting

and video enable DFF6 is reset.

stage. The negative-going pulse is taken from

A11Q3, and the positive-going pulse is taken from

c. Comparison Pulse Generation (fig. 8-4).

A11Q4. The outputs are applied to error gates

(1) Line-drive enable DFF2 and delay line

1 and 2 of the error detector (d below).

A6DL1. The line-drive enable DFF1 controls the

d. Error Detection Circuit.

decoder line-drive pulses. It permits only the F1

(1) Error gates 1 and 2 form a coincidence

reply pulses from video shaper DSS1 (receiver

circuit (fig. 8-5). They detect the coincidence of

sect ion) to pass. Initially set by the decode enable

reply-video pulses with those generated by com-

pulse, the 0 output (A9Q6) of linedrive enable

parison pulse shaper DSS2. Error gate 1 is con-

DFF1 is low and the 1 output (A9Q7) is high. In

nected to the normally low 1 output of video shaper

this state, the 1 output enables line-drive gate 1,

DSS1 and comparison pulse shaper DSS2. Error

and the positive F1 reply pulse from DSS1 is then

gate 2 is connected to the normally high (0) out-

gated. The gated pulse is coupled by line-drive gate

puts of these shapers Error gate 1 will normally

2 and delay-line driver A10Q7 to delay line

be in an on state, while gate 2 will be in an off state.

A6DL1, and fed back to reset DFF1 for the pur-

Also because both gate outputs are connected to-

pose of disabling line-drive gate 1. As the pulse

gether, an effective zero-reference output is estab-

flows down A6DL1, 12 information pulses, an F2

lished. With this arrangement, a change in state of

pulse and an identity pulse are developed. Each

only one gate causes the common output to go high.

information pulse is coupled by an emitter fol-

One gate must be off while the other gate is on to

lower to the respective CODE selection switch (A,

obtain the common zero-reference output. During

B, C, or D). Figure 8-4 shows these switches set

error detect ion, the gates perform as shown in the

for code 7777, and all 14 pulses of A6DLl are avail-

chart below. Reference time A represents the con-

able. During mode 1 identity test the delay-line

dition before any pulses are present. Reference time

I/P pulse output is used as an F1 pulse for com-

B indicates the condition caused by the arrival of

parison with the second F1 pulse of the second

the DSS1 pulse. Reference time C indicates the

pulse train. Two pulse trains are produced in the

coincidence of the pulses from DSS1 and DSS2.

delay line during this test since the delayed M1

Reference time D is the result of the trailing edge

pulse again sets DFF1. Thereby, the second F1

of the DSS2 pulse. Reference time E is the result.

only pulse is gated to the delay line, producing

of the trailing edge of the DSS1 pulse. Two posi-

the second group of information pulses and the F2

tive pulses are produced during reference times

pulse. During emergency tests this operation is

A through E.

extended, because four F1 replay pulses are used

to obtain the necessary train plus three sets of F1

Error gate 1 input Error gate 2 input

Refer

and P2 pulses The M1 pulse sets DFF1 each time

ence time DSS1 DSS2

DSS1 DSS2

Common output level

to permit gating of each subsequent F1 reply

A----- High High Low Low

Zero reference.

Low

pulse. In this test three I/P pulse outputs of the

H i g h High Low

High.

B - - - - - - Low Low

High High Zero referance.

delay line are used as the last three F1 comparison

D - - - - Low

High High LOW

High.

pulses. All pulses are applied to delay-line ouput

E----- LoW L o w

High High Zero reference.

2-22

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