Readout Circuit

P3 (last) interrogation pulse. Either a trigger from

(2) A typical reply pulse and its acceptable

spacing test limits are illustrated in figure 2-13 un-

read delay DSS5 (fig. 8-5) or a pulse from the error

der the Accept, condition column. Assume the C1 re-

detection circuit causes a change in state.

ply pulse arrives early. Under these conditions, er-

(2) Read delay DSS5 is triggered by video en-

ror gate 2 is disabled by the Cl reply pulse. Its out-

able delay DSS4 and produces a negative, 150-mi-

put then causes the zero-reference level to go high.

crosecond pulse at its 0 output. The trailing edge of

The duration of this condition depends on the actual

this pulse is gated by the readout gate when error

position of the reply pulse. If this pulse is missing,

blanking DFF2 is reset. When a reply is correct, this

the period will be 0.5 microsecond. If the pulse is

trigger sets DFF5, since it is initially in a reset

present, the period equals the deviation in pulse

state. The 1 output then goes high until the next de-

spacing from the nominal value. When the pulses at

code-enable pulse resets DFF5. This set period is

relatively long. If a reply is incorrect, the error de-

error gate 1 coincide, its output goes low. Thus, the

common output returns to the zero reference since

tection circuit sets DFF5 before the read-delay trig-

the gate 2 output is high. The duration of each re-

ger arrives. Since DFF5 is now set, the arrival of the

sultant positive error pulse for an accept condition

read-delay trigger causes it to go in a reset state;

is within 0.15 microsecond, and that for a reject

therefore, a relatively long reset state is estab-

condition is greater than 0.35 microsecond. These

lished. The 1 output of DSS5 is coupled to the reply

conditions are sensed for a readout ((3) below).

evaluator (f below) through MODE switch

(3) The leading edge of each positive error

A15S5-B. The reply evaluator senses the state of

pulse, developed by error gates 1 and 2, triggers

DFF5 by this output and provides a test indication

pulse generator DSS3 (fig. 8-5). Pulse generator

after a predetermined period. Read delay DSS5 also

DSS3 produces a negative-going 0.35-microsecond

inhibits receiver video gate 2 after 150 microsec-

pulse for each trigger. The error pulses are also gat-

onds (para 2-14b).

f. Reply Evaluator. The reply evaluator (fig. 8-5)

ed by error gate 3 and coupled by inverter A11Q9

and Q10 to error gate 4. Note that error gate 3 is in-

senses the number of correct replies within approxi-

hibted during the first F1 pulse time of each type

mately 50 prf periods (approximately .1 second). It

of reply (para 2-5d). Error pulses will arrive at error

then provides either a rejector an accept output, de-

gate 4 in coincidence with the negative 0.35-micro-

pending on the information received from the read-

second pulse from DSS3. If the duration of each

out circuit. A voltage integrator consisting of re-

positive error is less than the negative 0.35-micro-

sistor A12R18 and capacitor A12C8 is used to sense

second pulse from DSS3, error gate 4 remains off.

the output from readout memory DFF5. Schmitt

When either positive error pulse duration is greater

trigger A12Q51Q6 is controlled by the voltage inte-

than 0.35 microsecond, error gate 4 is gated on (fig.

grator. This trigger circuit has 0 (A12Q5) and 1

2-13). The negative pulse output of error gate 4 sets

(A12Q6) outputs. Control A12R19 is preadjusted

readout memory DFF5.

for a trigger level corresponding to a specific charge

e. Readout Circuit.

level of A12C8. The state of readout memory DFF5

(1) The readout circuit effectively provides the

during 50 prf periods determines the charge-dis-

results of each interrogation receiver cycle to the re-

charge cycle of the voltage integrator. When a reply

ply evaluator (f below). The state of readout mem-

is correct, the high (1) output of DFF5 causes the in-

ory DFF5 is the result of each test cycle and pro-

put inverter (A12Q4) to conduct for a comparatively

tides a readout of the reply evaluator. Readout

long period. The junction of resistors A12R17 and

memory DFF5 is a flip-flop multivibrator consisting

A12R18 will go low and capacitor A12C8 dis-

of transistors A12Q2 and A12Q3. When DFF5 is in

charges through A12R18. When 80 percent or more

a reset state, the 1 output is low and A12Q3 is con-

replies are correct during 50 prf periods, A12C8 dis-

ducting. The flip-flop multivibrator is initially reset

charges to a level that causes the 1 out-

by the decode-enable pulse produced by the encoder

Change 4

2-23