Mode 1 identity and emergency tests

TM 11-6625-667-45/NASHIPS 0969-249-8010/NAVAIR 16-30APM123-2/TO 33A1-3-367-22

identity tests, line-drive enable DFF1 and counter

DFF3/DFF4 during all modes except mode C.

DFF3/DFF4 control video enable DFF6. The 1

The reset operation for mode C is initiated by a

outputs of DFF1 and DFF3 are connected to the

25-microsecond delayed M3 timing pulse from de-

input of the train+ I/P reset gate. The output of

lay line A6DL1. Functioning of the video reset

this reset gate is connected through the MODE

operation and the means of obtaining the M1 and

and FUNCTION switches to the reset (C1) input

M3 timing pulses are described in (1) through

of video enable DFF6. The 22-microsecond de-

(4) below. Functioning of the. comparator-pulse

generator is provided in c below.

layed M1 pulse simultaneously triggers the

counter and sets DFF1. Since both circuits were

(1) M1/M3 timing pulses. Line-drive enable

in a reset state, their 1 outputs go high. The train

DFF1, initially set by the decode-enable pulse,

+ I/P reset gate is gated on and its output goes

provides the positive enabling voltage to line-

high. This action does not affect DFF6 since its

drive gate 1 (fig. 8-4). An F1 positive pulse from

reset (C1) input requires a negative-going signal.

video shaper DSS1 (para 2-13c) is then gated by

The high 1 output of DFF1 also enables line-drive

line-drive gate 1 and inverted. The resultant nega-

gate 1. Approximately 24 microseconds after the

tive pulse is gated and inverted by line-drive gate 2

F1 pulse, an I/P pulse arrives and is gated by line-

to provide a positive output pulse coupled by

drive gates 1 and 2. The positive output of gate 2

delay-line driver A10Q7 to drive delay line

is coupled by delay-line driver A10Q7 to reset

A6DL1. The positive pulse is also routed to reset

DFF1. Thus, the enabling voltage to the reset gate

line-drive enable DFF1. This action causes the 1

goes low and causes the train + I/P reset gate out-

output of DFF1 to go low, thereby, removing the

put to go low. This action, in turn, resets video

enabling voltages from line-drive gate 1. For all

enable DFF6 and ends the receiver gate period by

modes, except mode C, 22 microseconds after the

removing the enabling voltage from video gate 2.

pulse is applied to A6DL1, the pulse is coupled by

(4) Mode 1 identity and emergency tests

MODE switch A15S5-H to M1/M3 amplifier

(fig. 8-3). During mode 1 identity and emergency

A10Q8/A10Q9. The 22-microsecond delayed posi-

tests, counter DFF3/DFF4 is used to reset video

tive output of this circuit is called the M1 pulse.

enable DFF6. The 1 output of DFF3 and 0 output

The trailing edge of the positive M1 pulse again

of DFF4 are connected to the mode 1 I/P reset

sets line-drive enable DFF1, and triggers DFF3

gate for mode 1 identity tests. The 1 outputs of

of the counter. During mode C, the 25-microsecond

both counter sections are connected to the emer-

tap is coupled by MODE switch A15S5-H to the

gency gate. The gate output is connected to the

M1/M3 amplifier. This timing pulse is identified

reset (C1) input of DFF6 through the FUNC-

as M3 and is used to reset video enable DFF6 dur-

TION switch. Since a mode 1 identity reply con-

ing mode C tests.

sists of two pulse training two line-drive pulses are

(2) Systems tests. During all system tests, ex-

counted in this operation. In emergency operation,

rept mode C, the action of line-drive enable DFF1

four line-drive pulses are counted. The first 22-

only is used to conclude the receiver gate period.

microsecond delayed M1 pulse triggers the coun-

When DFF1 is set by the trailing edge of the posi-

ter and sets DFF1 as in the other tests described

tive M1 pulse. its 1output (A9Q7) goes high and

above. In this state, the counter section DFF3 1

its 0 output (A9Q6) goes low. The negative-going

output. is high and the DFF4 0 output is high,

0 output is coupled by MODE switch A15S5 and

For mode 1 identity operations, this establishes a

FUNCTION switch A15S6 to reset video enable

high output through the mode 1 identity reset

DFF6 (fig. 8-3). In this state, the DFF6 1

gate, at the reset (C1) input of video enable

(A9Q2) output is low and disables video gate 2,

DFF6. Then, 22 microseconds later the second Ml

concluding the receiver gate period. During mode

pulse causes the DFF3 1 output to go low. This

C tests the M3 timing pulse (delayed 25 micro-

act ion triggers counter section DFF4 and causes

seconds) resets DFF6 and thereby disables video

its 0 outputs to go low. The gating voltage is re-

gate 2.

(3) Identity (except mode 1). During the

moved from the mode 1 identity reset gate and

2-21

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