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T.O. 12P4-2APX-192
NAVAIR 16-35TS1843-1
TM 11-6625-1646-25
high. This will repeat for 60 usec, then the clock gate (A2A4)
module would decrease at a rate proportional to the repetition
is cleared to stop the clock pulses at the output of A2A3B (pin
rate of the incoming replies; until a level is reached to force
11). The negative-going transitions of the clock pulse will start
A3Q9 into cut off. The output of A3Qll is applied to the lamp
the ripple-thru counter counting. The positive going transitions
enable OR gate. The resulting output will energize the lamp
of the clock pulse and the duration of the pulse when it is high
driver circuit which turns the indicator lamp on.
will be applied to pin 9 of A2A1OC (clock output enable NAND
5-15. The Monitor mode is initiated by placing the RAD TEST-
MON switch on the control unit in the MON position.  As
5-19.  When a negative-going (low) transition of the clock
mentioned previously, this will ground the switch lead to the
pulse is applied to flip-flop A2A5A, pin 1, the output of pin 6
power supply through a diode and place the test set in an
goes low and pin 5 goes high.  The positive-going (high)
energized state. With the mode switches in the OUT position,
transition of the clock pulse has no effect on the flip-flop. On
the mode generator is deactivated and a +5 volts forward bias
the next low transition of the clock pulse (one usec after the
CR1 of AlAlA5 and back bias the step recovery diode CR1 of
first), the outputs at pins 6 and 5 are reversed (high and low,
AlAlA4, thus preventing any RF transmission during the
respectively) therefore causing the output at pin 5 to go high
Monitor mode.  The theory of operation of the comparator,
for one usec and low for one usec, while the output at pin 6 is
power detector, and bracket decoding circuits in the Monitor
the opposite of that at pin 5. The low from A2A5A, pin 5, is
mode is the same as that of the In-Flight Test mode.
applied to pin 13 of flip-flop A2A5B, causing the output of pin 9
5-16.  The remaining circuitry, the reply evaluator, can be,
to go high. As with A2A5A, the positive-going (high) excursion
divided into two distinct operations, the In-Flight Test mode
has no effect on the flip-flop. Two usec after the first low, the
evaluator (which has been discussed previously) and the
next low causes the output at pin 9 to go low and a two usec
Monitor mode evaluator. If the output of NAND gate, A4A3C,
pulse is generated.  Flip-flops A2A6B, A2A6A, A2A7B and
is a negative pulse, A3Q3 is turned off for the duration of the
A2A7A operate in the same manner as A2A5A and A2A5B.
pulse and will return to the normal state (on) until another
The duration of the pulses generated by A2A6B, A2A6A,
pulse is applied to A3Q3. After six or more pulses have been
A2A7B and A2A7A are four, eight, 16, and 32 usec,
applied to A3Q3, A3Q4 will energize, as a result of the
respectively, and form a set of binary spaced pulse trains (see
charging action within the Monitor mode evaluator. The output
of A3Q4 will change the state of the flip-flop (A3Q5, A3Q6)
5-20. The high outputs of A2A5A, A2A5B, A2A7B and A2A7A
producing an output from A3Q6. The output of A3Q6 is applied
(A, B, E, and F, respectively, figures FO-1 and 5-1) are applied
to the lamp enable OR gate. The output of A3Q5 is fed back
to A2A9A, the time enable NAND gate, and inverted to a low.
to the Monitor mode evaluator which will keep A3Q3 on and
The low output of A2A9A is then applied to A2A9B, inverted to
prevent any incoming pulse from retriggering A3Q4 for a
a high and in turn, applied to A2A1B, pin 10, A2A1OA, pin 13
minimum of two seconds. At the end of this time duration.
and A2A3C, pin 5. The high output of A2A6B (D, figures FO-1
A3Q4 will energize again (due to the feedback from A3Q5) and
and 5-1) is applied to A2A1OA, pin2 and pin 1 of A2A3D, the
turn A3Q6 off, thus turning the indicator lamp off.
sync time enable NAND gate. The other input to A2A3D, pin
2, is the high from A2A6A (C, figures FO-1 and 5-1). With
5-18. MODE GENERATOR (A2) (See figure FO-2). Since the
both inputs to A2A3D being high, the resultant low output is
operation of all four In-Flight modes (Modes 1, 2, 3/A and C)
inverted by A2A2F. The high output from A2A2F completes
are similar, a detailed step by step analysis of mode 1
the enablement of A2A3C, the sync enable NAND gate, which
operation will be covered only. With a low signal applied to pin
occurs three usec after the clock enable NAND gate, A2A3B,
2 of A2A1A (mode enable NAND gate) the resulting high
is enabled. Immediately after the sync is enabled, the output
signal (pin 6) is applied to A2A3A, pin 10. The positive-going
of A2A6A (C, figures FO-1 and 5-1), goes high and stays high
transition of the output of A2Q2 (PRF generator pulse) is also
for four usec. During these four usec A2A5B (B) output goes
applied to A2A3A at pin 9. The two high signals combined
low for two usec and then back to high for two usec; the output
enable A2A3A The resulting low signal is routed to pin 13 of
of A2A5A (A) goes low and then high, once every two usec.
flip-flop A2A4. A2A4, initial state, has a high output at pin 8
These high outputs of A2A5A, and A2A5B along with the high
and a low output at pin 9. The low input pulse at A2A4, pin 13,
from A2A7A (E), and A2A7B (F) enable A2A9A and appear at
triggers A2A4, changing the outputs at pins 8 and 9 to low and
A2A1OA pin 13 as a high. At this same time A2AlOA, pin 1 is
high, respectively. The low output at A2A4 (pin 8) is routed to
high (output of A2A6A (C)) as is pin 2 (output of A2A6B (D)).
A3Q7 (paragraph 5-28). The high output of A2A4 (pin 9) is fed
With all inputs to A2A1OA high, a low output is produced;
to A2A3B (pin 13) (clock enable NAND gate). The high output
thus, four usec after the sync is enabled, the zero reference
applied to A2A3B (pin 13) and the high output of A2Q3,
pulse is enabled.
applied to pin 12 enables A2A3B. When the clock enable gate
5-21. Immediately after the zero reference pulse is enabled,
is held on by the high pulse applied to pin 13 from A2A4, the
the outputs of A2A6B and A2A6A (D and C figures FO-1 and
resultant output at pin 11 of A2A3B will now follow the 1 MHz
5-1) applied to A2A8A pins 10, and 11, go high for eight and
clock. The output at pin 11 of A2A3B will be pulses, at the
four usec respectively.
clock rate, going from a high level to a low level and then to a

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