DETAILED CIRCUIT ANALYSIS - TM-11-6625-1646-250022

T.O. 12P4-2APX-192

NAVAIR 16-35TS1843-1

TM 11-6625-1646-25

A4R7. The output from the collector of A4Q1 is also a

During the first two usec, the output of A2A5B (B) applied to

negative pulse developed across A4R5. If the input to A4Q1 is

A2A8A, pin 12, is low, then goes high for two usec. During the

greater than the input to A4Q2, the difference is a negative

last two usec, the output of A2A5A (A) goes high for one usec

pulse on the collector of A4Q1 and is applied to the base of

and low for one usec, with the high enabling A2A8A. The

A4Q3. If the input amplitude to A4Q2 is greater than that to

resultant low is inverted by A2A8B and the high applied to

A4Q1, there will be no pulse output present at the collector of

mode 1 enable NAND gate A2A9C, pin 3. At this time, the

A4Q1. When there is a pulse it is amplified by A4Q3 and

signal levels applied to A2A9C. pins 1, 2, and 4 are high and

applied to the base of A4Q4 and again amplified. The output at

with the high from A2A8B applied. A2A9C is enabled. Thus.

the collector of A4Q4 is now a positive pulse which is routed to

three usec after the zero reference pulse. the mode 1 pulse is

a monostable multivibrator (A4A6). A4A6 develops a 0.1 usec

generated.

pulse which is then applied to NAND gate A4A3B, pin 13.

5-22. The low output from A2A9C is fed to, and inverted to a

5-25.

The power and frequency comparator is also a

high by, A2A9D and then applied to A2A1OC pin 11. The

differential amplifier made up of A4Q9 and A4Q10. The

output of A2AlOB, applied to A2A1OC pin 10 Is high (when

operation of the frequency power comparator is similar to the

one or more inputs to a NAND gate are low, the resultant

operation of the power and VSWR comparator. A4Q10

output is always high). and the signal level on pin 9 becomes

receives its information from the frequency detector. The

high enabling A2A1OC. The inverted output, a low, is then

negative output pulse of the differential amplifier is taken from

applied to a pulse shaper (A2Q4 and A2Q5). A2Q4 is

the collector of A4Q10. when the input amplitude applied to

normally conducting and A2Q5 is used to stabilize the D.C.

A4Q10 is greater than that applied to A2Q9. The output of

bias. The low signal applied to the base of A2Q4 will turn

A4Q10 is amplified by A4Qll and A4Q12 and then applied to

A2Q4 off. At the same time, A2C5 is discharged by the

NAND gate A4A3B, pin 1.

conduction of A2A1OC. When the clock pulse changes to a

5-26. The power level detector circuit is a Schmitt trigger

low, the output of A2A1OC at pin 8 goes high. A2C5 is now

composed of A4Q13 and A4Q14. When the input to the base

able to charge through A2R7 and through the internal

of A4Q13 reaches a positive threshold, which is preset by RF

resistance of A2A1OC for a period of time; until a level is

IN control A1R2, A4Q13 will trigger and apply a negative

reached, when A2Q4 starts to conduct. This extended time is

power monitor pulse to the base of A4Q14 which, in turn,

used to set the pulse width to 0.83 usec. The 0.83 usec pulse

inverts the power monitor pulse. The positive power monitor

is applied to the base of A2Q6 causing an output across

pulse is then applied to the base of A4Q15 and inverted and

emitter resistor A2R13. The resistor and capacitor network

amplified. A4Q16 amplifies and inverts the resulting negative

(A2R14, A2R15. A2C6 and A2C7) provides for D.C. isolation

output pulse from A4Q15. With power setting being satisfied,

to the RF generator while supplying a video pulse of proper

the positive pulse is then applied to decode NAND gate

characteristics. Commutating capacitor A2C7 allows for fast

A4A3A, pin 11 in the bracket decoding network.

rise time, while A2C6 isolates the D.C. A2C6 also provides a

5-27. The bracket decoding network is activated by the

negative spike on the trailing edge of the output pulse. This

positive power monitor pulse from the collector of A4Q16. The

negative spike back biases the RF modulator diode between

positive power monitor pulse is routed to trigger gate A4A1B,

pulses thereby reducing any residual continuous waste signals

pin 5, inverted and applied as a low (negative pulse) to A4A2

from the RF generator.

(monostable multivibrator). The high output of A4A2 (pin 6), a

5-23. When A2A7B is triggered (31 usec from time zero) the

positive 19 usec pulse is routed to inverter A4A1C. The

high output from pin 5 (F) is applied to the reset enable NAND

negative 19usec pulse output of A4A1C is then stretched by

gate, A2A1OB, pin 3. The output of A2A7B. pin 5 stays high

A4R39 and A4C18 to 24 usec and inverted by A4A1D. The

for 32 usec. 16 usec after A2A7B, pin 5, goes high, the output

high output of A4A1D is then inverted by A4A1A to A low. The

of A2A7A pin 9 goes high for 16 usec and is applied to

low 24 usec pulse is routed back to trigger gate A4AlB to

A2A1OB, pin 4; pin 5 of A2AIOB goes high 13 usec later

prevent a power monitor pulse from enabling A4A1B for a 24

(output of A2A8D) and is enabled. The inverted output, a low,

usec period. The low output of A4A2 (pin 1) is routed to

is applied to A2A1OC causing A2A1OC output to go high. The

A4A3A, pin 10.

low output of A2A1OB is also routed to flip-flops A2A4 and

5-28. The low 24 usec pulse output of A4A1A is also routed to

A2A5A through A2A7B, causing the flip-flops to clear. This

the base of A4Q17, cutting off A4Q17. When A4Q17 is in

sequential operation of the mode generator assembly (A2)

cutoff, the low path to ground through A4CR1 is removed and

takes place every 30 usec after A2A3B has been enabled.

the ringing oscillator, A4Q5 and associated components, is

5-24. COMPARA1'OR-DECODER (A4) (See figure FO-3).

now able to oscillate. The sinusoidal 540 KHz output of the

The power and VSWR comparator network is a differential

ringing oscillator is isolated by emitter follower A4Q6 and

amplifier circuit. composed of A4Q1 and A4Q2. The output of

routed to the base of A4Q18. The negative-going portions of

the video power detector is applied to the base of A4Q1. The

the 540 KHz signal are clipped off by A4CR4 at the base of

input to the base of A4Q2 Is the VSWR pulse received from

A4Q18. The remaining portion of the 540 KHz signal is

the VSWR control (AlR1).

A1R1 determines the pulse

shaped and inverted. The output at the collector of A4Q18, a

amplitude of the pulse applied to A4Q2 base. The output from

seven volt peak-to-peak negative-going

the collector of A4Q2 is a negative pulse developed across

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