Typical Block Digital Circuit

TM 11-5895-1012-10

3-13. Typical

Digital Circuit

patch panel jack set to the receive pair of the user

(fig. FO-13)

equipment.

(3) Patch cord No. 8, from jacks 3 and 4, row 2,

a. General. In this example of a black digital circuit,

module A, panel 1 to jacks 3 and 4, row 3, module A,

the Universal Digital Patch Panel jack sets are pro-

panel 2 connects the receive clock to the ring (R) lead

grammed with a group 4 module in the send circuit

of the patch panel jack set. The R lead is normal-

and a group 5 module in the receive circuit. Refer to

through wired to the R1 lead of the jack set and cabled

paragraph 3-156 and c for patch panel circuit details.

to jack 3, row 4, module A, panel 2 of the IDF. The

This circuit is cross-connected in IDF bay 1.10. The lo-

same patch cord also connects the receive clock return

cal equipment (EQUIP side of circuit) is cabled to mod-

to a common tie point and to jack 4, row 4, module A,

ule A of panel 6. The line equipment (LINE side of cir-

panel 2 of the IDF.

cuit) is cabled to module A of panel 1. The jack sets of

(4) Patch curd No. 11, from jacks 3 and 4, row 4,

the Universal Digital Patch Panel are cabled to module

module A, panel 2 to jacks 3 and 4, row 2, module A,

A of panel 2. Optional devices are not used, but con-

panel 6 completes the receive clock circuit to the local

nections that could be used are shown.

equipment.

b. Send Circuit. To complete the send circuit, dual-

d. Red Digital Circuit. A red digital circuit is con-

plug, cross-connect patch cords are installed as fol-

nected in a similar manner and will not be discussed.

lows:

(1) Patch cord No. 4, from jacks 1 and 2, module

3-14. Universal Digital

A, panel 6 to jacks 1 and 2, row 2, module A, panel 2.

a. Description. The front

This connects the transmit data output of the user

tains 24 sets of four jacks with a switch and lamp that

equipment to pin 5 of patch panel connector C-l. This

is associated with each jack set. There are three rows

is the jack sets tip (T1) lead, which is normal-through

of identification (ID) card holders. The card holders al-

wired to pin 1 (tipT) of patch panel connector C-l. Pin

low the circuit and equipment connected to the circuit

1 of C-1 is cabled to jack 1 of row 1 in module A, panel

to easily be identified. The rear of each patch panel has

2. The transmit data return is also cross-connected

two connectors (Cl and C2), that are used to connect

with patch cord No. 4, and is connected to a common

the jack set circuits (through connectors J1 and J2) to

tie point.

the IDF. Below the connectors are 24 program mod-

(2) Patch cord No. 1, between jacks 1 and 2, row 1,

ules. Between the connectors and program boards

module A, panel 2 and pins 1 and 2, row 1, module A,

there is a jack set ID strip indicating the jack set asso-

panel 1 completea the transmit data and transmit data

ciated with each program board.

return to the line equipment.

b. Circuit Functions (fig. FO-15). Each jack set is

(3) Patch cord No. 5, from jacks 3 and 4, row 1,

connected (through a flexible printed circuit board) to

module A, panel 6 to jacks 3 and 4, row 2, module A,

a program board. The board is programmed by a pro-

panel 2 connects the transmit clock through the R1

gram module (containing jumpers) to set up an opera-

and R leads of the patch panel jack set, to jacks 3 and

tional circuit. The functions that may be performed by

4. row 1. module A. panel 2 of the IDF. The transmit

the circuits are given in (1) through (6) below. Two typ-

clock return is also connected to the common tie point

ical circuits for which modules are available are dis-

through patch cord No. 5.

cussed in paragraph 3-15.

(4) Patch cord No. 2, from jacks 3 and 4, row 1,

(1) Provides a normal through path for digital sig-

module A, panel 2 to jacks 3 and 4, row 1, module A,

nals when no patches are made.

panel 1 completes the transmit clock and transmit

(2) When patching in a replacement sending de-

clock return to the line equipment.

vice, the patching configuration will terminate the in-

c. Receive Circuit. To complete the receive circuit,

terrupted sending equipment in an impedance equal to

dual cross-connect patch cords are installed as follows:

the input impedance of the receiving device.

(1) Patch cord No. 7, from jacks 1 and 2, row 2,

(3) When patching in a replacement receiving de-

module A, panel 1 to jacks 1 and 2, row 3, module A,

vice the patching configuration will hold the interrupt

panel 2 connects the receive data line to the tip (T) lead

ed receiving equipment with a holding voltage or cur-

set. The T lead is nor-

rent equal to the mark voltage or current transmitted

1 lead of the patch pan-

by the sending device.

row 4, module A, panel

(4) The patch panel will perform the above func-

rd connects the receive

tions for all the following types of digital signals:

(a) Low level 6VDC send and receive.

(b) Low level 3VDC send and receive.

(c) High level polar or neutral send and receive.

(d) Low level receive with associated timing.

3-11