DETAILED CIRCUIT DISCUSSION-CONT. - TM-11-5805-688-14-10275

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

When the +12V Reg output increases to +14.4 volts or

generation of the over temp signal to shut down the

the +5V Reg output increases to +6 volts, the same

power supply when an over-temperature condition exists.

procedure is repeated through diode CR2 or CR4 to

to be shut off and disable the clock

cause switch

5-637. When the SELF TEST switch on the front panel

generator.

is set to the ON position, the self-test signal is applied to

the power supply. The self-test signal biases on Q14 in

the input circuit of AR1-12. When Q14 is on, an under

5-635. In the under voltage condition,

the output

volt- age condition is simulated and ARl-10 causes the

voltage level from AR3-10 decreases when the -12V Reg

local and remote alarm signals to be generated until the

output de- creases to -10.8 volts. This condition causes

self- test signal is removed from the input of Q14.

current to flow through CR3 to place a negative potential

on the inverting input of AR2-1. This causes the voltage

5-638. The 18-kHz output from 18-kHz oscillator AR4 in

level from AR2-12 to increase and bias Q1 into

Q2.

As a result, Q1 produces the

the clock generator is applied to switch Q4. Switch Q4 in

conduction and cutoff

low- level local alarm signal (PSF-) and Q2 produces the

turn, is switched on and off at the 18-kHz rate. The

pulses from Q4 are applied through inverter U2-11 to

high-level remote alarm signal (PSFR). Potentiometer

inverter U2-3 and the B clock flip-flop U1l-5. The B clock

R27 is factory set to establish the bias on voltage for

flip-flop, in turn, produces 9-kHz, B clock pulses to one-

AR2-12 for an under- voltage condition. When the +12V

shot multivibrator U3-10 in the +12-volt regulator circuit.

Reg output decreases to +10.8 volts or the +5V Reg

The B clock signals are also applied to the +5-volt

output decreases to +4.5 volts, the same procedure is

regulator circuits on card A2. The 18-kHz pulses are

repeated through diode CR1 or CR3 to force AR2-12 to

bias Q1 into conduction and cutoff Q2 to produce the two

routed through inverter U2-3 to A-clock flip-flop Ul-9

alarm signals.

(figure 5-49) to produce the 9-kHz clock pulse's.

5-636. When the temperature in the power supply

increases to 205F, thermostat switch S1 on the power

5-639. In the following discussion, the -12V Reg output

supply chassis closes. When S1 closes, a signal ground

is assumed to be decreasing to a less-negative voltage

(HOT-) path to the front panel is completed and causes

level. The same function also represents the condition

over temp signal (IPSE-) to be generated by the circuits

where the +12V Reg output decreases to a less-positive

on the front panel. The over temp signal is applied to the

voltage level. The decreasing -12-volt input to AR6-1

power supply as an inhibit signal to the negative input of

causes a lower output from AR6-12 that is applied to

AR1-10. This inhibit signal causes AR1-10 to bias switch

AR6-7. The non-inverting input to AR6-6 is connected to

Q4 into conduction and disable the clock generator and

the +4.77V Reg voltage. The inverting input receives the

shut down the overall power supply. The over temp

negative- going input and causes the output voltage from

signal from the front panel holds the power supply in the

AR6-10 to increase. Thus the output voltage from AR6-

shut down condition until the POWER CONTROL

10 applied to AR7-4 becomes a higher threshold voltage

ON/OFF switch on the front panel is set to-the OFF and

level for the stage.

then back to the ON position. Removing the TEMP

SHUTDOWN jumper on the front panel inhibits the

Change 2 5-174