Diagnostic Circuits

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

The high error output enables AND gate U23-8, causing

The minor frame counts from both minor frame

link error rate signal LLER to be generated and light the

generation circuits are identical when the equipment is in

LINK ERROR RATE indicator on the front panel. At the

a no-error condition. Therefore, diagnostic comparator

same time, remote alarm relay K3 energizes and initiates

U22 produces an A=B output that holds flip-flop Ull-6

remote link error rate signals LERRC1 and LERRC2.

output high. When an error condition exists, the minor

The output from AND gate U24-10 applied to AND gate

frame counts applied to U22 do not compare and the

U23-3 is inhibited by the low-level ST1-signal applied to

A=B output is low. As a result, the output of Ull-6 goes

the second input to AND gate U23-3. AND gate U23-3 is

low and generates loss-of- frame error signal LOMFC-

used only in the diagnostic self-test function to test the

the next time signal DEOS2B- occurs. In the self-test

ERD logic. When the count from U25'reaches zero,

mode, flip-flop Ull-6 is held in the clear condition to

AND gates U24-10, U24-13, and U23-11 combine to

generate signal LOMFC-.

produce an inhibit signal to AND gate U17-6. With AND

gate U17-6 inhibited, no further count down occurs in

U25.

5-559. When the SELF TEST switch on the front panel

is set to the on(up) position, self-test signal ST1- goes

5-557. Remote Alarm Circuits. The diagnostic circuits

low and sets latch U18-11, U18-3. The high signal from

in the power supply generate power supply fail signals

U18-11 enables one input of AND gate U23-3. At the

PSFR and -12 PSFR to energize remote alarm relay K6

same time, the low output from U18-3 clears U33,

when a power supply failure occurs. Energizing relay K6

forcing error up/down counter U25 to count down and

generates a closed-loop condition through remote power

generate an error signal from AND gate U24-10 to AND

supply fail signals PSFC1 and PSFC2. that are routed to

gate U23-3. When AND gate U23-3 is enabled, rate

the REMOTE ALARMS connector on the rear panel.

detector diagnostic error signal DERD- is generated. At

The functional operation of each of the remote alarm

the same time, signals ST1- and ST2- are applied to all

relays K1 through K6 is basically the same. A card

the cards in the multiplexer set to set all diagnostic

failure in the multiplexer set is applied as signal FAIL to

circuits in the self-test mode. In the self-test mode

relay K1. An out-of-tolerance condition in the multiplexer

remote alarm relays K1 through K6 are energized to

function is applied as out-of-tolerance signal LMOOT to

produce error indications. When the SELF TEST switch

relay K2. Relay K3 is energized when the count in the

is set to the off (down) position, signal STS is applied to

output of error up/down counter U25 decreases to a

reset latch U18-11, U18-3. The output from U18-3 goes

count of three. Relay K4 is energized by multiplexer

high and enables AND gate U26-3 in the reset circuits.

loss-of-timing signal LOTRA- or by demultiplexer loss-of-

The low output from U26-3 causes error reset signals

timing signal DLOF. Relay K5 is energized by a loss of

ERST-, ERST, DERRS, DERRS- and reset temperature

frame sync signal DFS.

alarm signal RTA to be generated and reset all the

diagnostic circuits in the multiplexer set to their off state,

5-558. Diagnostic Circuits.

Shift register U13,

assuming that the multiplexer set is in a no-error

counters U14 and U6, and comparator U15 form the

condition.

diagnostic minor frame generation circuits that are

identical to the functional minor frame generation circuits.

5-151