Error Rate Detector (ERD) Circuits - TM-11-5805-688-14-10251

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

Assuming that the incoming minor frame count pattern is

applied to U46 and U41. When signal DNSE is applied

not deliberately changed, adequate count up sequences

to U46 and U41, signals DENS0, DENS1, and DENS3

are developed between random no-compares to hold the

are applied through the selectors to U33. When both

count above zero in the error up/down counter so that

signals are missing during word 28, signals DENAO,

consecutive minor frame counts can be properly

DENA1, and DENA3 are applied to U33. In a no-error

generated from the minor frame counter.

condition, three ones are applied to the preset inputs of

overhead error counter U33 during word 28. Since the

MSB preset input to U33 is always high, a count of 15 is

5-553. Error Rate Detector (ERD) Circuits. The three

preset into U33. Therefore, the TC output of U33 goes

divide-by-10 registers (U9, U2, and U1) are clocked by

high and applies a count up signal to AND gate U16-8

end-of-scan signal DEOS2B- during words 1 through 23.

and a count down inhibit through inverter U32-10 to AND

Each output from the three registers plus word 24

gate U17-6.

through word 29 signal DW2429- are applied to the input

of one AND gate in threshold control logic U10. One

5-555. For each error count applied through the error

error rate threshold switch is set to enable one of the four

-1

count selectors to the preset input of overhead error

AND gates in U10. Enabling switch 10 effectively

counter U33, one count down pulse is effectively

allows each DEOS2B- signal generated during words 1

generated to AND gate U17-6 through inverter U32-10.

through 23 to clock a count into divide-by-16 threshold

-2

Assuming an error count of four, a count of 11 is preset

counter U4. Switch 10 allows one out of 100 DEOS2B-

-3

into counter U33 during word 28. (Input from U41 to U33

signals to clock U4. Switch 10 allows one out of 1000

-4

is low and all other inputs to U33 are high.) Therefore,

DEOS2B- signals to clock U4. Switch 10 allows one out

four DEOS2B- signals are required to reach the TC

of 10,000 DEOS2B- signals to clock U4. In turn, counter

count out of U33.

U4 clocks out one count up pulse for each 16 times it is

clocked. Each time a terminal count of 15 is obtained, a

5-556. Each time AND gate U16-8 is enabled, the low

count up enable pulse is applied from U4 to AND gate

output is applied as a count up pulse to counter U25. In

U16-8. At the same time, a count down inhibit pulse is

turn, each time AND gate U17-6 is enabled, a count

applied through inverter U3-10 to AND gate U17-6. The

down pulse is applied to counter U25. AND gate U16-8

time during which a TC count is not present, an inhibit

is enabled when a count up signal is applied from U4 and

count up signal is applied to AND gate U16-8 to prevent

U33, the count in U25 is less than 15, and signal

any count up from occurring, and the signal applied

DEOS2B- is applied to the SB card. AND gate U17-6 is

through inverter U3-10 is applied as a count down enable

enabled when a count up signal is applied from U4 and

signal to AND gate U17-6.

U33, the count in U25 is not zero, and signal DEOS2B- is

applied to the SB card. In an error environment, AND

5-554. The error counts produced on the FS card for

gate U24-10 produces a high error output when the

the three stuff commands are applied to error count

count in U25 decreases to a count of three or less.

selectors U46 and U41 during word 28. Error count

signals DEPSO, DEPS1, and DEPS3 are applied

through the selectors to U33 when signal DPSE is

5-150