Error Rate Detector (ERD) Circuits-CONT.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

Signal DNSE causes error count signals DENSO,

count of one or more is present in the counter. In normal

DENS1, and DENS2 to be applied to the counter. The

operation, when a sufficient number of error bits is

absence of both signals DPSE and DNSE during word

detected and the error up/down counter is decremented

28 causes signals DENAO, DENA1, and DENA2 to be

to a count of three or less, AND gate U24-10 generates a

applied to the counter. Word 28 signal DW28 presets

link error signal to the remote alarm circuits and to the

the selected error count (between zero and seven) into

front panel.

the over- head error counter. The outputs from the three

selector circuits are inverted; therefore, in a no-error

5-544. The error rate threshold circuits establish the bit

condition, three ones are applied to the overhead error

error rate that can be tolerated in a given number of data

counter. The count eight preset input to the counter is

bits before a link error condition is indicated by lighting

always high (connected to +5 volts).Therefore, a no-error

the LINK ERROR RATE indicator on the front panel.

condition presets a count of 15 into the counter and

Four error rate threshold switches on the ERD card

causes the terminal count (TC) output to go high and

provide for the selection of one of four threshold levels.

-1,

-2,

-3,

-4

The switches are marked 10 10 10 and 10 and

present a count up input to the error up/down counter.

correspond to a threshold level of one error in 10 bits,

one error in 100 bits, one error in 1000 bits, or one error

5-542. An error count of seven from the three selectors

in 10, 000 bits. In normal operation, the divide-by-16

to the overhead error counter appears as three zeros so

threshold counter divides down the pulses from the

that the next preset count into the counter is a count of

selected threshold input. Each output pulse from the

eight. As a result, seven count down pulses are

counter is a count up enable pulse that is applied to AND

produced while the next seven DEOS2B- signals

gate U16-8 in the count up input to the error up/down

increment the overhead error counter output to produced

counter. When a pulse is not generated, the output from

the TC out- put. Therefore, in all conditions, the

the counter is a count down enable signal to AND gate

overhead error counter produces one count down pulse

U17 in the count down input to the error up/down

for each error count applied to the three selectors for the

counter. When a count up enable is applied to AND gate

given stuff command being monitored.

U16-8 at the time that a TC count is present from the

overhead error counter, a count up pulse increments the

5-543. AND gate U16-8 in the count up input of the

error up/down counter if the counter output is less than

error up/down counter is enabled by count up signals

15. In turn, a count up enable from the divide-by-16

from the divide-by-16 threshold counter and by the

threshold counter applied at the time that a TC count is

overhead error counter, signal DEOS2B-, and an enable

not present from the overhead error counter will nullify

signal from AND gate U16-6. When the error up/down

one count down pulse by a low-level inhibit applied

counter contains a count of 15, AND gate U16-6 inhibits

through inverter U3 to AND gate U17. Therefore, when

AND gate U16-8 to hold the maximum counter output to

the count from the error up/down counter is less than 15,

15. AND gate U17 in the count down input of the error

each count up pulse from the divide-by-16 threshold

up/down counter is enabled by count down signals from

counter causes one count up to be accomplished, or the

the divide-by-16 threshold counter and by the overhead

count up pulse effectively nullifies one count down pulse

error counter, signal DEOS2B-, and an enable signal

from being applied to the counter.

from AND gate U23. When the counter contains a count

of zero, AND gate U23 inhibits AND gate U17 until a

5-145